A RTN variation tolerant guard band design for a deeper nanometer scaled SRAM screening test: Based on EM Gaussians mixtures approximations model of long-tail distributions

This paper discusses, for the first time, how the guard band (GB) designs for screening-test should be unprecedentedly changed when the shift-amount of voltage-margin variations after screening becomes larger than that of before screening. Since the increasing-pace of time-dependent (TD) random telegraph noise (RTN) is a 1.4x faster than non-TD variations of random dopant fluctuation (RDF), the effect of TD-variations on the GB-shift will become larger than that of non-TD in coming process generations like 15nm and beyond. Three types of amplitude-ratios of RTN to RDF (RTN/RDF: 0.25, 1, 4) are assumed in this discussion. The screening yield-loss impacts, made by: 1) larger ratio of RTN/RDF and 2) approximation-error of longer tailed RTN distribution, are discussed. It has been shown that yield-loss (chip-discarding) by screening test may become crucial issues if RTN could not be reduced because the yield-loss can become 5-orders of magnitude times larger than that for 40nm when RTN/RDF=1. It has been found that the required accuracy-level of statistical model for approximating RTN tail-distributions significantly increases as RTN/RDF gets close to 1. Intolerable yield-loss can be increased by 6-orders of magnitude due to its errors of GB designs. A fitting method to approximate a longer tailed RTN Gamma-distribution by simple Gaussian mixtures model (GMM) is proposed. The proposed concepts are 1) adaptive segmentation of the long tailed distributions such that the log-likelihood of GMM in each partition is maximized and 2) copy and paste fashion with an adaptive weighting into each partition. It has been verified that the proposed method can reduce the error of the fail-bit predictions by 2-orders of magnitude while reducing the iterations for EM step convergence to 1/16 at the interest point of the fail probability of 10-12 which corresponds to the design point to realize a 99.9% yield of 1Gbit chips.