Y. Uchida, Shihai He, Xin Yang, Qing Liu, T. Yoshimasu
{"title":"5 ghz波段线性CMOS功率放大器集成电路，具有新颖的集成线性放大器，用于WLAN应用","authors":"Y. Uchida, Shihai He, Xin Yang, Qing Liu, T. Yoshimasu","doi":"10.1109/RFIT.2012.6401673","DOIUrl":null,"url":null,"abstract":"In this paper, novel linearization technique is proposed to realize a 5-GHz band linear CMOS power amplifier IC for WLAN application. The novel linearizer which consists of a diode-connected PMOS bias circuit and a PMOS varactor connected in parallel with an NMOS amplifier is effectively to suppress the gain compression and phase distortion of the power amplifier. A CMOS power amplifier IC is designed, fabricated and fully tested using TSMC 0.13-μπι CMOS technology. With these proposed techniques, the measurement results show a third-order IMD improvement of 9 dB over wide output power range and the maximum improvement of 18 dB. The power amplifier IC exhibits an output PldB of 19.5 dBm and a power gain of 9.5 dB at an operation voltage of 3.3 V.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"5-GHz band linear CMOS power amplifier IC with a novel integrated linearizer for WLAN applications\",\"authors\":\"Y. Uchida, Shihai He, Xin Yang, Qing Liu, T. Yoshimasu\",\"doi\":\"10.1109/RFIT.2012.6401673\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, novel linearization technique is proposed to realize a 5-GHz band linear CMOS power amplifier IC for WLAN application. The novel linearizer which consists of a diode-connected PMOS bias circuit and a PMOS varactor connected in parallel with an NMOS amplifier is effectively to suppress the gain compression and phase distortion of the power amplifier. A CMOS power amplifier IC is designed, fabricated and fully tested using TSMC 0.13-μπι CMOS technology. With these proposed techniques, the measurement results show a third-order IMD improvement of 9 dB over wide output power range and the maximum improvement of 18 dB. The power amplifier IC exhibits an output PldB of 19.5 dBm and a power gain of 9.5 dB at an operation voltage of 3.3 V.\",\"PeriodicalId\":187550,\"journal\":{\"name\":\"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIT.2012.6401673\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2012.6401673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
5-GHz band linear CMOS power amplifier IC with a novel integrated linearizer for WLAN applications
In this paper, novel linearization technique is proposed to realize a 5-GHz band linear CMOS power amplifier IC for WLAN application. The novel linearizer which consists of a diode-connected PMOS bias circuit and a PMOS varactor connected in parallel with an NMOS amplifier is effectively to suppress the gain compression and phase distortion of the power amplifier. A CMOS power amplifier IC is designed, fabricated and fully tested using TSMC 0.13-μπι CMOS technology. With these proposed techniques, the measurement results show a third-order IMD improvement of 9 dB over wide output power range and the maximum improvement of 18 dB. The power amplifier IC exhibits an output PldB of 19.5 dBm and a power gain of 9.5 dB at an operation voltage of 3.3 V.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
