Stabilization techniques of power hardware-in-the-loop simulation with time delay compensation

In power electronics, Power Hardware-in-the-loop Simulation (PHILS) which consists of Hardware part and Digital Simulator part has attracted attention. This is the very useful tool to shorten development time and to simplify verification under complicated condition. However, it is known that instability is caused by the time delay between Digital Simulator and Hardware. This paper applies two methods to manage instability. One is model-base Smith method, and the other is the model-free Fictitious Reference Iterative Tuning (FRIT) method. Experimental results indicate that two methods are effective in compensating the time delay and stabilizing PHILS system.