{"title":"一种用于CMOS APS表征的测试结构","authors":"T. Elkhatib, S. Moussa, H. Ragaie, H. Haddara","doi":"10.1109/ICM.2003.238501","DOIUrl":null,"url":null,"abstract":"A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64/spl times/64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timing and control digital circuits as well as correlated double sampling have been built on a 0.6 /spl mu/m CMOS process. The test methodology and preliminary simulation results are presented.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A test structure for characterization of CMOS APS\",\"authors\":\"T. Elkhatib, S. Moussa, H. Ragaie, H. Haddara\",\"doi\":\"10.1109/ICM.2003.238501\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64/spl times/64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timing and control digital circuits as well as correlated double sampling have been built on a 0.6 /spl mu/m CMOS process. The test methodology and preliminary simulation results are presented.\",\"PeriodicalId\":180690,\"journal\":{\"name\":\"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2003.238501\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2003.238501","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
提出了一种CMOS APS图像传感器的测试结构。设计了单独的光电二极管和像素以及64/spl倍/64个有源像素的图像传感器阵列,具有可选的线性或对数操作模式。除了片上时序和控制数字电路以及相关双采样外,测试芯片还包括这些功能,这些功能已建立在0.6 /spl μ m CMOS工艺上。给出了试验方法和初步仿真结果。
A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64/spl times/64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timing and control digital circuits as well as correlated double sampling have been built on a 0.6 /spl mu/m CMOS process. The test methodology and preliminary simulation results are presented.