A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications

In this paper the implementation of a low power high speed 4-bit Binary Search ADC (BS-ADC) is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the latch-based conventional comparators. The reported structure of the ADC occupies an active area of 0.0157 mm2 and consumes 127 μW of average power while operating with an input frequency (fin) of 5 MHZ, and a supply voltage of 1.8Volt. For this proposed architecture, the maximum sampling rate is obtained as 0.2 GSPS. At 0.2 GSPS sampling rate, the Signal to Noise plus Distortion Ratio (SNDR) is found to be 20.84 dB, yielding the Effective Number of Bits (ENOB) as 3.2 bit.