用于55nm CMOS工艺ESD保护的高保持电压LVTSCR

2019 8th International Symposium on Next Generation Electronics (ISNE) Pub Date : 2019-10-01 DOI:10.1109/ISNE.2019.8896559

K. Yang, Jizhi Liu, Zhiwei Liu

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引用次数: 3

摘要

提出了一种提高LVTSCR保持电压用于静电放电保护的有效方法，并在55 nm外延CMOS工艺中进行了验证。该方法通过去除NW中的STI和调整NMOS栅极长度来提高保持电压。此外，它还可以为ESD保护提供良好的鲁棒性。测量结果表明，保持电压可提高66%左右。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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LVTSCR with High Holding Voltage for ESD Protection in 55nm CMOS Process

A effective method to enhance the holding voltage of LVTSCR for electrostatic discharge (ESD) protection applications has been proposed and verified in a 55 nm epitaxial CMOS process. The proposed method improves the holding voltage by removing the STI in NW and adjusting the NMOS gate length. In addition, it can provide an good robustness for ESD protection. Measured results show that the holding voltage can be improved 66% approximately.

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2019 8th International Symposium on Next Generation Electronics (ISNE)

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