优化宽高比以提高标准6T(S6T)-SRAM单元的功率和噪声裕度

Saranga Bhavani, Lipika Gupta, Ashish Sachdeva, T. Sharma
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摘要

随着计算功耗降低技术的不断进步,对低功耗、可靠、高效的静态随机存取存储器(SRAM)设计的需求不断上升。电源电压缩放是减小SRAM单元功耗同时保持高静态噪声裕度的首选技术。然而,这种增强产生了几个后果,包括延迟的增加,因此,整体高功率延迟产品。本文考虑了一个标准的6T(S6T)-SRAM单元,通过改变上拉、下拉和接入晶体管的宽高比,在0.5 V到1 V的不同电源电压下分析其性能参数。分析了不同的Cell ratio (CR)和Pull-up ratio (PR)下的读写时延、读写功率和功率延迟积(PDP)。该分析有助于找到45纳米技术节点供电电压为0.7 V时的最佳功率延迟产品。
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Optimization of the aspect ratio to enhance the power and noise-margin of a standard 6T(S6T)-SRAM cell
The demand for low-power, dependable and efficient static random-access memory (SRAM) design has risen as a result of the continuous progress in computational power reduction technologies. Supply voltage scaling is the preferable technique to minimize power dissipation in SRAM cells while keeping a high value of static noise margins. However, such enhancement creates several consequences, including an increase in delay and, therefore, overall high-power delay product. In this paper, a standard 6T(S6T)-SRAM cell is considered for the analysis of its performance parameters by changing the aspect ratio of the pull-up, pull-down, and access transistors for the varying supply voltage of 0.5 V to 1 V. The read/write delay, read/write power, and power delay product (PDP) are analyzed for different Cell Ratios (CR) and Pull-up Ratios (PR). This analysis helped to find the optimum power delay product for the supply voltage of 0.7 V for the 45nm technology node.
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