Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10059652
M. Sivasakthi, P. Radhika
Current Mode Logic (CML) is generally utilized for high-speed circuits. This is a differential digital logic used to design inverters, buffers and gates, as well as the board-level signaling of digital data. Among the various types of CML circuits, in various digital circuit designs, MOS Current Mode Logic (MCML) is generally implemented. This logic can also be used to design registers and memory units. In this paper, a novel MOS CML circuit is designed using a flipped voltage follower-based tri-state circuit for Inverter/Buffer and AND/NAND logic and also for the high-speed multiplexer. The proposed MCML logic gate is analyzed using the Cadence virtuoso tool in 45 nm technology at 1V power supply and a temperature of 27°C. The results are verified with Monte Carlo simulations using a histogram plot. The process variations for different corners are simulated and compared for the conventional, existing and proposed structures under 45 nm CMOS technology. The result proves that the proposed circuit provides high performance and operates in a high-speed environment.
{"title":"A High-Speed MCML Logic Gate and Multiplexer Design in 45 nm CMOS Technology","authors":"M. Sivasakthi, P. Radhika","doi":"10.1109/ICERECT56837.2022.10059652","DOIUrl":"https://doi.org/10.1109/ICERECT56837.2022.10059652","url":null,"abstract":"Current Mode Logic (CML) is generally utilized for high-speed circuits. This is a differential digital logic used to design inverters, buffers and gates, as well as the board-level signaling of digital data. Among the various types of CML circuits, in various digital circuit designs, MOS Current Mode Logic (MCML) is generally implemented. This logic can also be used to design registers and memory units. In this paper, a novel MOS CML circuit is designed using a flipped voltage follower-based tri-state circuit for Inverter/Buffer and AND/NAND logic and also for the high-speed multiplexer. The proposed MCML logic gate is analyzed using the Cadence virtuoso tool in 45 nm technology at 1V power supply and a temperature of 27°C. The results are verified with Monte Carlo simulations using a histogram plot. The process variations for different corners are simulated and compared for the conventional, existing and proposed structures under 45 nm CMOS technology. The result proves that the proposed circuit provides high performance and operates in a high-speed environment.","PeriodicalId":205485,"journal":{"name":"2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116901718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10059799
Sanjit V K, Nirmitha S, R. Jayachandran, Vijayadurga P, Yashaswini G Y
The footstep power generation system using different configurations of piezo-sensors are analyzed in this paper. Energy generated by human walking, jumping and running is used as a source of energy which is converted to an equivalent electrical energy using piezoelectric effect. Experimental analysis of circular type piezoelectric sensors connected in different configurations- series, parallel and combination of series-parallel and sensors of various diameters show that series-parallel combination generates more voltage and is stable compared to other configurations. Circular type piezo sensor model is developed in the COMSOL Multiphysics simulator which shows near performance with the experimental results.
{"title":"Parametric analysis of piezoelectric-sensor array in foot step power generation system","authors":"Sanjit V K, Nirmitha S, R. Jayachandran, Vijayadurga P, Yashaswini G Y","doi":"10.1109/ICERECT56837.2022.10059799","DOIUrl":"https://doi.org/10.1109/ICERECT56837.2022.10059799","url":null,"abstract":"The footstep power generation system using different configurations of piezo-sensors are analyzed in this paper. Energy generated by human walking, jumping and running is used as a source of energy which is converted to an equivalent electrical energy using piezoelectric effect. Experimental analysis of circular type piezoelectric sensors connected in different configurations- series, parallel and combination of series-parallel and sensors of various diameters show that series-parallel combination generates more voltage and is stable compared to other configurations. Circular type piezo sensor model is developed in the COMSOL Multiphysics simulator which shows near performance with the experimental results.","PeriodicalId":205485,"journal":{"name":"2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121240342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electromyography on the surface of the body (EMG) is used to examine the electrical activity of the muscles. In order to evaluate human fitness, it is now essential to extract qualitative features from EMG signals. Fourteen distinct time-domain and frequency-domain features have been derived for various hand movements. In this study, EMG signals collected during six distinct hand activities have been analysed by using statistical tests, such as the t-test, sign-rank test and the analysis of variance, to determine the degree to which specific properties vary. The hand movement under study was dumbbell up, dumbbell down and hand gripper with both hands i.e two sets of data for each movement. The results show that there is no such difference for the dumbbell activity considering either up or down movement except for a few features regardless of the hand used. Although the non-significant result was found for all features considering both left-hand griper and right-hand griper. But the majority of the features show there is enough evidence (p<0.05) showing significant difference when considering up and down movement for both hands' dumbbell activity. Similarly, there was a significant difference ($p < 0.5$) in the majority case for all features considering all dumbbell activity at a time using analysis of variance.
{"title":"Statistical Analysis for EMG Extracted Time and Frequency Domain Features during Different Dumbbell Activity","authors":"Prashant Kumar, Vivek Ranjan, Ashis Kumar Das, Suman Halder","doi":"10.1109/ICERECT56837.2022.10059837","DOIUrl":"https://doi.org/10.1109/ICERECT56837.2022.10059837","url":null,"abstract":"Electromyography on the surface of the body (EMG) is used to examine the electrical activity of the muscles. In order to evaluate human fitness, it is now essential to extract qualitative features from EMG signals. Fourteen distinct time-domain and frequency-domain features have been derived for various hand movements. In this study, EMG signals collected during six distinct hand activities have been analysed by using statistical tests, such as the t-test, sign-rank test and the analysis of variance, to determine the degree to which specific properties vary. The hand movement under study was dumbbell up, dumbbell down and hand gripper with both hands i.e two sets of data for each movement. The results show that there is no such difference for the dumbbell activity considering either up or down movement except for a few features regardless of the hand used. Although the non-significant result was found for all features considering both left-hand griper and right-hand griper. But the majority of the features show there is enough evidence (p<0.05) showing significant difference when considering up and down movement for both hands' dumbbell activity. Similarly, there was a significant difference ($p < 0.5$) in the majority case for all features considering all dumbbell activity at a time using analysis of variance.","PeriodicalId":205485,"journal":{"name":"2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124800835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10060382
Pujashree, Latha H.K.E, Dayananda Ys
DFT (Design for Testability) is an important additional logic that is inserted in an ASIC across the functional logic to aid post-production testing of the chip and to evaluate the faults in silicon that could have caused due to imperfections in fabrication process. DFT gasket verification is required because DFT is again implemented by Engineers which is prone to human errors. In today's ever-growing complexity of Systems-on-Chip (SoC)s, insufficient or inefficient DFT support due to poor specification, implementation or lax design procedures can suddenly become essential to meet market deadlines and delivering products under budget and tight schedules. The goal of this project is to provide a comprehensive, systematic, and completely automated approach for verification of DFT gaskets. The gaskets have to work predictably being cycle-accurate and in sequence as per expectation. Any deviation from the specification could have serious consequences including chip failure, subsequently causing billions of $ cost. An adoptable, random, predictable, cycle-accurate and robust infrastructure had to be built to verify the DFT gaskets so as to ensure the design is bug free. To be reusable, we have chosen UVM as methodology for environment and SystemVerilog as language for verification. Developing the scenarios in testcases and subsequently checkers for the same was carried out. Here DFT gaskets are On-chip clock controller and SRAM. Working of checkers is to compare the actual data expected data. Exceed application was used for connecting to server, Synopsys VCS was used for simulation and Synopsys Verdi tool for debugging.
DFT (Design for Testability，可测试性设计)是一个重要的附加逻辑，它跨功能逻辑插入ASIC中，以帮助芯片的后期测试，并评估由于制造过程中的缺陷可能导致的硅中的故障。DFT垫片验证是必需的，因为DFT再次由工程师实施，容易出现人为错误。在当今日益复杂的片上系统(SoC)中，由于规范不佳、实施或设计程序松懈而导致的DFT支持不足或效率低下，对于满足市场最后期限和在预算和紧迫的时间表下交付产品来说，可能突然变得至关重要。该项目的目标是提供一种全面、系统和完全自动化的方法来验证DFT垫片。垫片必须工作可预测的周期准确，并按顺序预期。任何与规格的偏差都可能导致严重的后果，包括芯片故障，随后造成数十亿美元的损失。必须建立一个可采用的、随机的、可预测的、周期精确的和健壮的基础设施来验证DFT垫圈，以确保设计没有错误。为了便于重用，我们选择了UVM作为环境方法，SystemVerilog作为验证语言。在测试用例中开发场景，并随后对其进行检查。这里的DFT垫圈是片上时钟控制器和SRAM。检查人员的工作是比较实际数据和预期数据。使用Exceed应用程序连接服务器，使用Synopsys VCS进行仿真，使用Synopsys Verdi工具进行调试。
{"title":"Implementation of Checkers for DFT Gaskets using SV/UVM","authors":"Pujashree, Latha H.K.E, Dayananda Ys","doi":"10.1109/ICERECT56837.2022.10060382","DOIUrl":"https://doi.org/10.1109/ICERECT56837.2022.10060382","url":null,"abstract":"DFT (Design for Testability) is an important additional logic that is inserted in an ASIC across the functional logic to aid post-production testing of the chip and to evaluate the faults in silicon that could have caused due to imperfections in fabrication process. DFT gasket verification is required because DFT is again implemented by Engineers which is prone to human errors. In today's ever-growing complexity of Systems-on-Chip (SoC)s, insufficient or inefficient DFT support due to poor specification, implementation or lax design procedures can suddenly become essential to meet market deadlines and delivering products under budget and tight schedules. The goal of this project is to provide a comprehensive, systematic, and completely automated approach for verification of DFT gaskets. The gaskets have to work predictably being cycle-accurate and in sequence as per expectation. Any deviation from the specification could have serious consequences including chip failure, subsequently causing billions of $ cost. An adoptable, random, predictable, cycle-accurate and robust infrastructure had to be built to verify the DFT gaskets so as to ensure the design is bug free. To be reusable, we have chosen UVM as methodology for environment and SystemVerilog as language for verification. Developing the scenarios in testcases and subsequently checkers for the same was carried out. Here DFT gaskets are On-chip clock controller and SRAM. Working of checkers is to compare the actual data expected data. Exceed application was used for connecting to server, Synopsys VCS was used for simulation and Synopsys Verdi tool for debugging.","PeriodicalId":205485,"journal":{"name":"2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125153533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10060739
Humera Aqeel, Anupriya Kamble
The increase in online and social media connection has made it simple for hate speech and insulting language to spread. Cyberbullying is the phrase used to describe such online abuse, insults, and assaults. It has become difficult to detect such unauthorized material due to the huge number of user-generated content. Deep neural networks are being used more often by academics to identify cyberbullying than regular machine learning algorithms because to their many benefits over them. Machine learning has several uses in text categorization. Hence, it is fundamental to distinguish and sort CB utilizing profound learning (DL) models in informal organizations to avoid this pattern. FSSDL-CBDC is a fresh out of the plastic new methodology for informal communities that joins profound learning and element subset determination. The SSA-DBN model has demonstrated to be more exact than different calculations with a 99.983% precision rate. Generally speaking, the trials' discoveries showed that the FSSDL-CBDC strategy performs better compared to the contending systems in various ways.
{"title":"A Hybrid Classifier of Cyber Bullying Detection in Social Media Platforms","authors":"Humera Aqeel, Anupriya Kamble","doi":"10.1109/ICERECT56837.2022.10060739","DOIUrl":"https://doi.org/10.1109/ICERECT56837.2022.10060739","url":null,"abstract":"The increase in online and social media connection has made it simple for hate speech and insulting language to spread. Cyberbullying is the phrase used to describe such online abuse, insults, and assaults. It has become difficult to detect such unauthorized material due to the huge number of user-generated content. Deep neural networks are being used more often by academics to identify cyberbullying than regular machine learning algorithms because to their many benefits over them. Machine learning has several uses in text categorization. Hence, it is fundamental to distinguish and sort CB utilizing profound learning (DL) models in informal organizations to avoid this pattern. FSSDL-CBDC is a fresh out of the plastic new methodology for informal communities that joins profound learning and element subset determination. The SSA-DBN model has demonstrated to be more exact than different calculations with a 99.983% precision rate. Generally speaking, the trials' discoveries showed that the FSSDL-CBDC strategy performs better compared to the contending systems in various ways.","PeriodicalId":205485,"journal":{"name":"2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123699164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10060170
S. Thiru, Hina Hashmi, S. Hemavathi, Daxa Vekariya, Arvind Kumar Pandey, Wael M. F. Abdel-Rehim
Millions many sensors will be connected to the Internet via the Networks of Things (IoT), enabling new mobile cloud technologies and products. With the introduction of IoT, future Internet of Vehicle (IoV) will replace the present Auto Informal Services (Van - to - Driver), where customers may place orders for various services by integrating their cars, sensors, and tablets to a huge network. Vehicular Cloud Computing (VCC) is merely being imagined with the goal of supplying traffic services that enhance our daily traveling in order to provide Routes with broadband service. These plans include resources and support the expansion of the Internet of Things (IoT), which is a crucial component of IoV. The utilization of Vehicular Cloud (VC), however, is necessary for ITS (Intelligent Transportation System) to properly support a top travel service (VC). In order to acquire data for the benefit of ITS, we integrate the novel VCC technique in this study. We show via modeling results that a flexible VC may provide useful data collection with just a small percentage of autos involved.
数以百万计的传感器将通过物联网(IoT)连接到互联网，从而实现新的移动云技术和产品。随着物联网的引入，未来的车联网(IoV)将取代目前的汽车非正式服务(Van - to - Driver)，客户可以通过将他们的汽车、传感器和平板电脑集成到一个巨大的网络中来订购各种服务。车载云计算(VCC)的目标仅仅是提供交通服务，增强我们的日常出行，以便为路线提供宽带服务。这些计划包括资源和支持物联网(IoT)的扩展，物联网是车联网的关键组成部分。然而，车辆云(vehicle Cloud, VC)的利用是智能交通系统(ITS)正确支持顶级出行服务(VC)的必要条件。为了更好地获取数据，我们将新的VCC技术整合到本研究中。我们通过建模结果表明，灵活的风险投资可能只涉及一小部分汽车，就能提供有用的数据收集。
{"title":"Vehicular Cloud Data Collection for Intelligent Transportation Systems","authors":"S. Thiru, Hina Hashmi, S. Hemavathi, Daxa Vekariya, Arvind Kumar Pandey, Wael M. F. Abdel-Rehim","doi":"10.1109/ICERECT56837.2022.10060170","DOIUrl":"https://doi.org/10.1109/ICERECT56837.2022.10060170","url":null,"abstract":"Millions many sensors will be connected to the Internet via the Networks of Things (IoT), enabling new mobile cloud technologies and products. With the introduction of IoT, future Internet of Vehicle (IoV) will replace the present Auto Informal Services (Van - to - Driver), where customers may place orders for various services by integrating their cars, sensors, and tablets to a huge network. Vehicular Cloud Computing (VCC) is merely being imagined with the goal of supplying traffic services that enhance our daily traveling in order to provide Routes with broadband service. These plans include resources and support the expansion of the Internet of Things (IoT), which is a crucial component of IoV. The utilization of Vehicular Cloud (VC), however, is necessary for ITS (Intelligent Transportation System) to properly support a top travel service (VC). In order to acquire data for the benefit of ITS, we integrate the novel VCC technique in this study. We show via modeling results that a flexible VC may provide useful data collection with just a small percentage of autos involved.","PeriodicalId":205485,"journal":{"name":"2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122652364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10060517
Kavita Bhatt, S. M. Kumar
Digital Transformation is a new buzz word in industrial world which transforms the physical world into virtual space. It leverages the implementation of digital technologies to accelerate the growth of the industry/business. It refers to automation, digitalization of process, infrastructure, organization, management with the help of Industry 4.0 technologies like Cloud computing, 5G& 6G, analytics, Big data, Additive manufacturing, Artificial Intelligence, augmented reality, cyber-physical system, smart sensors, IoT Platforms, cloud computing. The field is continuously evolving and shaping the future of Medium, Small and micro industries (MSMEs). Digital Transformation (DX) provides opportunities and possibilities to MSMEs to accelerate their growth via recent disruption in technologies and its attached benefits. The industry is shifting towards virtual work from mechanized systems leveraging benefits of industry 4.0 practices like AI, big data, Intelligent network system, machine learning, strong network connection and making effective use of digital transformation. Since end users' requirements and consumption of goods keep increasing product industry 5.0 is gaining much attention which refers to the integration of Artificial Intelligence matching to the level of human capabilities. This paper discusses the evolution of industry 4 and emerging I4.0 technology, major drivers and factors impacting the implementation of I4.0 practices. It also covers the paradigm shift in how next-generation industry is getting shifted with the help of I5.0. It highlights the prospects of the development of technologies that is contributing to the transition of Industry 4.0 to Industry 5.0. This study provides a high-level overview of industry 4.0, its emergences and emerging technologies and transition from Industry 4.0 to Industry 5.0. This paper also highlights the main components of Industry 5.0 and how digital transformation can be moved from machine to human-machine collaboration.
{"title":"Way Forward to Digital Society – Digital Transformation of Msmes from Industry 4.0 to Industry 5.0","authors":"Kavita Bhatt, S. M. Kumar","doi":"10.1109/ICERECT56837.2022.10060517","DOIUrl":"https://doi.org/10.1109/ICERECT56837.2022.10060517","url":null,"abstract":"Digital Transformation is a new buzz word in industrial world which transforms the physical world into virtual space. It leverages the implementation of digital technologies to accelerate the growth of the industry/business. It refers to automation, digitalization of process, infrastructure, organization, management with the help of Industry 4.0 technologies like Cloud computing, 5G& 6G, analytics, Big data, Additive manufacturing, Artificial Intelligence, augmented reality, cyber-physical system, smart sensors, IoT Platforms, cloud computing. The field is continuously evolving and shaping the future of Medium, Small and micro industries (MSMEs). Digital Transformation (DX) provides opportunities and possibilities to MSMEs to accelerate their growth via recent disruption in technologies and its attached benefits. The industry is shifting towards virtual work from mechanized systems leveraging benefits of industry 4.0 practices like AI, big data, Intelligent network system, machine learning, strong network connection and making effective use of digital transformation. Since end users' requirements and consumption of goods keep increasing product industry 5.0 is gaining much attention which refers to the integration of Artificial Intelligence matching to the level of human capabilities. This paper discusses the evolution of industry 4 and emerging I4.0 technology, major drivers and factors impacting the implementation of I4.0 practices. It also covers the paradigm shift in how next-generation industry is getting shifted with the help of I5.0. It highlights the prospects of the development of technologies that is contributing to the transition of Industry 4.0 to Industry 5.0. This study provides a high-level overview of industry 4.0, its emergences and emerging technologies and transition from Industry 4.0 to Industry 5.0. This paper also highlights the main components of Industry 5.0 and how digital transformation can be moved from machine to human-machine collaboration.","PeriodicalId":205485,"journal":{"name":"2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114292226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10060859
Saranga Bhavani, Lipika Gupta, Ashish Sachdeva, T. Sharma
The demand for low-power, dependable and efficient static random-access memory (SRAM) design has risen as a result of the continuous progress in computational power reduction technologies. Supply voltage scaling is the preferable technique to minimize power dissipation in SRAM cells while keeping a high value of static noise margins. However, such enhancement creates several consequences, including an increase in delay and, therefore, overall high-power delay product. In this paper, a standard 6T(S6T)-SRAM cell is considered for the analysis of its performance parameters by changing the aspect ratio of the pull-up, pull-down, and access transistors for the varying supply voltage of 0.5 V to 1 V. The read/write delay, read/write power, and power delay product (PDP) are analyzed for different Cell Ratios (CR) and Pull-up Ratios (PR). This analysis helped to find the optimum power delay product for the supply voltage of 0.7 V for the 45nm technology node.
随着计算功耗降低技术的不断进步，对低功耗、可靠、高效的静态随机存取存储器(SRAM)设计的需求不断上升。电源电压缩放是减小SRAM单元功耗同时保持高静态噪声裕度的首选技术。然而，这种增强产生了几个后果，包括延迟的增加，因此，整体高功率延迟产品。本文考虑了一个标准的6T(S6T)-SRAM单元，通过改变上拉、下拉和接入晶体管的宽高比，在0.5 V到1 V的不同电源电压下分析其性能参数。分析了不同的Cell ratio (CR)和Pull-up ratio (PR)下的读写时延、读写功率和功率延迟积(PDP)。该分析有助于找到45纳米技术节点供电电压为0.7 V时的最佳功率延迟产品。
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Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10060185
U. K. Singh, N. Kumar
Given the volatile market prices and potential for declining fuel supplies, interest in electric vehicles has been exceptionally high. Electric vehicles are now a viable alternative, especially for short-distance travel, thanks to advances in battery technology and vital improvements in electrical motor efficiency. This study illustrates the use of Brushless DC (BLDC) motor technology in an electric car with a special focus on regenerative braking. Because of their great productivity and strength, BLDC motors are used more frequently in electric vehicles; nonetheless, a BLDC motor needs a fairly complex regulation to adapt to the inversion of the energy stream during the transition from the driving system to regenerative braking. In a BLDC motor, there are several methods for performing regenerative braking. According to the suggested approach, braking can be done by using various Stator voltages from a multi-cell battery system without the use of an additional DC assist converter with a complicated exchanging method or an ultra-capacitor.
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Pub Date : 2022-12-26DOI: 10.1109/ICERECT56837.2022.10060708
Manoj Kumar B C, Anil Kumar R J, Shashidhara D, P. M
Securing communication and information is known as cryptography. To convert messages from plain text to cipher text and the other way around. It is the process of protecting the data and sending it to the right audience so they can understand and process it. Hence, unauthorized access is avoided. This work suggests leveraging DNA technology for encrypt and decrypt the data. The main aim of utilizing the AES in this stage will transform ASCII code to hexadecimal to binary coded form and generate DNA. The message is encrypted with a random key. Shared key used for encrypt and decrypt the data. The encrypted data will be disguised as an image using steganography. To protect our data from hijackers, assailants, and muggers, it is frequently employed in institutions, banking, etc.
{"title":"Data Encryption and Decryption Using DNA and Embedded Technology","authors":"Manoj Kumar B C, Anil Kumar R J, Shashidhara D, P. M","doi":"10.1109/ICERECT56837.2022.10060708","DOIUrl":"https://doi.org/10.1109/ICERECT56837.2022.10060708","url":null,"abstract":"Securing communication and information is known as cryptography. To convert messages from plain text to cipher text and the other way around. It is the process of protecting the data and sending it to the right audience so they can understand and process it. Hence, unauthorized access is avoided. This work suggests leveraging DNA technology for encrypt and decrypt the data. The main aim of utilizing the AES in this stage will transform ASCII code to hexadecimal to binary coded form and generate DNA. The message is encrypted with a random key. Shared key used for encrypt and decrypt the data. The encrypted data will be disguised as an image using steganography. To protect our data from hijackers, assailants, and muggers, it is frequently employed in institutions, banking, etc.","PeriodicalId":205485,"journal":{"name":"2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123373208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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