{"title":"TTA-C2单片机通信控制器为时间触发协议","authors":"M. Ley, H. Grünbacher","doi":"10.1109/ICCD.2002.1106811","DOIUrl":null,"url":null,"abstract":"This paper describes the architecture and implementation of the first industrial single chip communication controller for the Time Triggered Protocol (TTP/C). TTP/C is an emerging communication protocol for fault-tolerant real time systems. Typical applications are safety-critical digital control systems such as drive-by-wire and fly-by-wire. We applied a VHDL based design flow to implement an application specific RISC core with several specialized peripheral blocks, RAMs, flash memory and analog cells. For production of the 27 mm/sup 2/ chip a 0.35 /spl mu/ Flash-CMOS technology is used Fully tested samples are already available and proved the design to be \"first time right\".","PeriodicalId":164768,"journal":{"name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"TTA-C2 a single chip communication controller for the time-triggered-protocol\",\"authors\":\"M. Ley, H. Grünbacher\",\"doi\":\"10.1109/ICCD.2002.1106811\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the architecture and implementation of the first industrial single chip communication controller for the Time Triggered Protocol (TTP/C). TTP/C is an emerging communication protocol for fault-tolerant real time systems. Typical applications are safety-critical digital control systems such as drive-by-wire and fly-by-wire. We applied a VHDL based design flow to implement an application specific RISC core with several specialized peripheral blocks, RAMs, flash memory and analog cells. For production of the 27 mm/sup 2/ chip a 0.35 /spl mu/ Flash-CMOS technology is used Fully tested samples are already available and proved the design to be \\\"first time right\\\".\",\"PeriodicalId\":164768,\"journal\":{\"name\":\"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-09-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2002.1106811\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2002.1106811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
TTA-C2 a single chip communication controller for the time-triggered-protocol
This paper describes the architecture and implementation of the first industrial single chip communication controller for the Time Triggered Protocol (TTP/C). TTP/C is an emerging communication protocol for fault-tolerant real time systems. Typical applications are safety-critical digital control systems such as drive-by-wire and fly-by-wire. We applied a VHDL based design flow to implement an application specific RISC core with several specialized peripheral blocks, RAMs, flash memory and analog cells. For production of the 27 mm/sup 2/ chip a 0.35 /spl mu/ Flash-CMOS technology is used Fully tested samples are already available and proved the design to be "first time right".