{"title":"600 MHz乱序执行的问题逻辑","authors":"J. Farrell, T. Fischer","doi":"10.1109/VLSIC.1997.623777","DOIUrl":null,"url":null,"abstract":"The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"81","resultStr":"{\"title\":\"Issue Logic For A 600 MHz Out-of-order Execution\",\"authors\":\"J. Farrell, T. Fischer\",\"doi\":\"10.1109/VLSIC.1997.623777\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.\",\"PeriodicalId\":175678,\"journal\":{\"name\":\"Symposium 1997 on VLSI Circuits\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"81\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1997 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1997.623777\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1997 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1997.623777","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.
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