用忆阻器横条阵列实现算术逻辑单元的内存重构

Dev Narayan Yadav, P. L. Thangkhiew
{"title":"用忆阻器横条阵列实现算术逻辑单元的内存重构","authors":"Dev Narayan Yadav, P. L. Thangkhiew","doi":"10.1109/CONECCT.2018.8482399","DOIUrl":null,"url":null,"abstract":"Current von-Neumann computing technology demands high capacity storage and high communication bandwidth to access data between storage and processing units. Memristor is a promising device that has the desirable properties using which in-memory computing can be performed in the storage unit. These properties of memristors can overcome the bottleneck faced by current von-Neumann architecture. In this paper, we provide a reconfigurable implementation of a 1-bit Arithmetic Logical Unit (ALU) using the memristor crossbar array. Enabling the configuration in system hardware will provide the functionality to use the same module of the system for multiple purposes and change the functionality of the module as per the requirement. The proposed design of the ALU provides functionality to perform the operations in the single module (memristor crossbar) and it is capable to add new operations as per the requirements. For the design of such ALUs, we use the MAGIC NOT and NOR gates. To validate the design we perform SPICE simulation of a half adder using Cadence Virtuoso.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Towards an In-Memory Reconfiguration of Arithmetic Logical Unit using Memristor Crossbar Array\",\"authors\":\"Dev Narayan Yadav, P. L. Thangkhiew\",\"doi\":\"10.1109/CONECCT.2018.8482399\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Current von-Neumann computing technology demands high capacity storage and high communication bandwidth to access data between storage and processing units. Memristor is a promising device that has the desirable properties using which in-memory computing can be performed in the storage unit. These properties of memristors can overcome the bottleneck faced by current von-Neumann architecture. In this paper, we provide a reconfigurable implementation of a 1-bit Arithmetic Logical Unit (ALU) using the memristor crossbar array. Enabling the configuration in system hardware will provide the functionality to use the same module of the system for multiple purposes and change the functionality of the module as per the requirement. The proposed design of the ALU provides functionality to perform the operations in the single module (memristor crossbar) and it is capable to add new operations as per the requirements. For the design of such ALUs, we use the MAGIC NOT and NOR gates. To validate the design we perform SPICE simulation of a half adder using Cadence Virtuoso.\",\"PeriodicalId\":430389,\"journal\":{\"name\":\"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)\",\"volume\":\"93 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CONECCT.2018.8482399\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONECCT.2018.8482399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

当前的冯-诺伊曼计算技术需要大容量的存储和高通信带宽来访问存储和处理单元之间的数据。忆阻器是一种很有前途的器件,它具有在存储单元中执行内存计算所需的特性。记忆电阻器的这些特性可以克服当前冯-诺伊曼结构所面临的瓶颈。在本文中,我们提供了一个1位算术逻辑单元(ALU)的可重构实现,使用忆阻器交叉棒阵列。启用系统硬件中的配置将提供将系统的相同模块用于多种目的的功能,并根据需求更改模块的功能。建议的ALU设计提供了在单个模块(忆阻交叉棒)中执行操作的功能,并且能够根据需求添加新的操作。对于这种alu的设计,我们使用了MAGIC NOT和NOR门。为了验证该设计,我们使用Cadence Virtuoso对半加法器进行了SPICE仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Towards an In-Memory Reconfiguration of Arithmetic Logical Unit using Memristor Crossbar Array
Current von-Neumann computing technology demands high capacity storage and high communication bandwidth to access data between storage and processing units. Memristor is a promising device that has the desirable properties using which in-memory computing can be performed in the storage unit. These properties of memristors can overcome the bottleneck faced by current von-Neumann architecture. In this paper, we provide a reconfigurable implementation of a 1-bit Arithmetic Logical Unit (ALU) using the memristor crossbar array. Enabling the configuration in system hardware will provide the functionality to use the same module of the system for multiple purposes and change the functionality of the module as per the requirement. The proposed design of the ALU provides functionality to perform the operations in the single module (memristor crossbar) and it is capable to add new operations as per the requirements. For the design of such ALUs, we use the MAGIC NOT and NOR gates. To validate the design we perform SPICE simulation of a half adder using Cadence Virtuoso.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Strain Dependent Carrier Mobility in 8 − Pmmn Borophene: ab-initio study Diameter Scaling in III-V Gate-All-Around Transistor for Different Cross-Sections Atomistic Study of Acoustic Phonon Limited Mobility in Extremely Scaled Si and Ge Films Optimal Token Bucket Refilling for Tor network Traffic Pattern Analysis from GPS Data: A Case Study of Dhaka City
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1