{"title":"用忆阻器横条阵列实现算术逻辑单元的内存重构","authors":"Dev Narayan Yadav, P. L. Thangkhiew","doi":"10.1109/CONECCT.2018.8482399","DOIUrl":null,"url":null,"abstract":"Current von-Neumann computing technology demands high capacity storage and high communication bandwidth to access data between storage and processing units. Memristor is a promising device that has the desirable properties using which in-memory computing can be performed in the storage unit. These properties of memristors can overcome the bottleneck faced by current von-Neumann architecture. In this paper, we provide a reconfigurable implementation of a 1-bit Arithmetic Logical Unit (ALU) using the memristor crossbar array. Enabling the configuration in system hardware will provide the functionality to use the same module of the system for multiple purposes and change the functionality of the module as per the requirement. The proposed design of the ALU provides functionality to perform the operations in the single module (memristor crossbar) and it is capable to add new operations as per the requirements. For the design of such ALUs, we use the MAGIC NOT and NOR gates. To validate the design we perform SPICE simulation of a half adder using Cadence Virtuoso.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Towards an In-Memory Reconfiguration of Arithmetic Logical Unit using Memristor Crossbar Array\",\"authors\":\"Dev Narayan Yadav, P. L. Thangkhiew\",\"doi\":\"10.1109/CONECCT.2018.8482399\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Current von-Neumann computing technology demands high capacity storage and high communication bandwidth to access data between storage and processing units. Memristor is a promising device that has the desirable properties using which in-memory computing can be performed in the storage unit. These properties of memristors can overcome the bottleneck faced by current von-Neumann architecture. In this paper, we provide a reconfigurable implementation of a 1-bit Arithmetic Logical Unit (ALU) using the memristor crossbar array. Enabling the configuration in system hardware will provide the functionality to use the same module of the system for multiple purposes and change the functionality of the module as per the requirement. The proposed design of the ALU provides functionality to perform the operations in the single module (memristor crossbar) and it is capable to add new operations as per the requirements. For the design of such ALUs, we use the MAGIC NOT and NOR gates. To validate the design we perform SPICE simulation of a half adder using Cadence Virtuoso.\",\"PeriodicalId\":430389,\"journal\":{\"name\":\"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)\",\"volume\":\"93 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CONECCT.2018.8482399\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONECCT.2018.8482399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Towards an In-Memory Reconfiguration of Arithmetic Logical Unit using Memristor Crossbar Array
Current von-Neumann computing technology demands high capacity storage and high communication bandwidth to access data between storage and processing units. Memristor is a promising device that has the desirable properties using which in-memory computing can be performed in the storage unit. These properties of memristors can overcome the bottleneck faced by current von-Neumann architecture. In this paper, we provide a reconfigurable implementation of a 1-bit Arithmetic Logical Unit (ALU) using the memristor crossbar array. Enabling the configuration in system hardware will provide the functionality to use the same module of the system for multiple purposes and change the functionality of the module as per the requirement. The proposed design of the ALU provides functionality to perform the operations in the single module (memristor crossbar) and it is capable to add new operations as per the requirements. For the design of such ALUs, we use the MAGIC NOT and NOR gates. To validate the design we perform SPICE simulation of a half adder using Cadence Virtuoso.