Analysis of Power Transfer Modeling for Three Dimension silicon chip’s using ThSV Technologies

Power transfer is expected to be major physical design concern in Three Dimension ICs due to higher energy density and package asymmetries. Three Dimension integrated circuits promise high bandwidth, low latency energy and a small form factor. To improve Three Dimension energy transfer different methods have been used in this paper. Analyzed the influence such as ThSV granularity, ThSV size, and spacing of controlled collapse chip connection (C4) and also dedicated energy transfer ThSVs. Investigated typical cylindrical or square metal filled ThSVs (Core ThSVs) for energy transfer. Three Dimension evaluation system is composed of quad internal chip multiprocessor, a memory cast and ACCL and it is evaluated using representative some SPEC bench marks traces. It is the detailed architectural level study of for Three Dimension energy transfer. Also this paper focuses on low energy and low skew timer interconnected points design and study of for ThSV based Three Dimension stacked silicon chip’s. Developed Three Dimension abstract tree generation based on the 3Dimensional method of means and medians (Three Dimension-MnM) method to determine the optimal count of ThSV’s to be used in the Three Dimension timer tree so that the overall energy dissipation is minimized. Provided the set of rules for Three Dimension energy transfer design and also the mathematical and statistical study of for energy transfer interconnected points of Three Dimension ICs.