Design of a 3/sup rd/ order CMOS sigma-delta modulator with faster conversion rates using zero-pole canceling technique

This paper proposes a new SDM (sigma delta modulator) architecture to improve conversion rates and SNR (signal-to noise ratio). The characteristic of the proposed SDM employs an adaptive clocking architecture which includes the first integrator with a 1 MHz clock and the second/third integrator with a 4 MHz clock. The SDM circuit with a 0.65 um CMOS process is simulated by both MATLAB and HSPICE. The simulation results illustrate that SNRs of the proposed SDM are increased by 2 dB @internal 1 bit ADC/DAC and 7 dB @3 bit and 5 bit compared with the conventional SDM.