A Novel Power Management Save-Restore Flow Architecture using Calibrated Ring Oscillator Clock Generation

This paper deals with the issue of system wake up latency as a consequence of power gating techniques. There are different architectures proposed to reduce the power inside the IPs (Intellectual property) like clock gating and power gating, Still system level IDLE power gating is a bigger concern. According to the nature of the system, multiple system states are created based on power and IDLE conditions. Another drawback of the power gating is system wake up latency which will be impacting the system performance. Here in this paper we have introduced an innovative way to reduce the system latency by a new power architecture flow with a calibrated ring oscillator clock and ran all power management operations on the newly generated clock. The overall impact in performance, power and area will also be discussed in this paper.