大型集成电路版图检查系统

Papers on Twenty-five years of electronic design automation Pub Date : 1988-06-01 DOI:10.1145/62882.62899

Kenji Yoshida, T. Mitsuhashi, Y. Nakada, Toshiaki Chiba, Kiyoshi Ogita, S. Nakatsuka

{"title":"大型集成电路版图检查系统","authors":"Kenji Yoshida, T. Mitsuhashi, Y. Nakada, Toshiaki Chiba, Kiyoshi Ogita, S. Nakatsuka","doi":"10.1145/62882.62899","DOIUrl":null,"url":null,"abstract":"This paper describes a new design rule checking system for LSI mask patterns. Major features of the system are a relatively small computing time needed, even for very large circuits (e.g. 10,000 elements), wide applications to a variety of fabrication processes, due to its functional flexibility, and minimized spurious errors.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A layout checking system for large scale integrated circuits\",\"authors\":\"Kenji Yoshida, T. Mitsuhashi, Y. Nakada, Toshiaki Chiba, Kiyoshi Ogita, S. Nakatsuka\",\"doi\":\"10.1145/62882.62899\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a new design rule checking system for LSI mask patterns. Major features of the system are a relatively small computing time needed, even for very large circuits (e.g. 10,000 elements), wide applications to a variety of fabrication processes, due to its functional flexibility, and minimized spurious errors.\",\"PeriodicalId\":354586,\"journal\":{\"name\":\"Papers on Twenty-five years of electronic design automation\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Papers on Twenty-five years of electronic design automation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/62882.62899\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Papers on Twenty-five years of electronic design automation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/62882.62899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

本文介绍了一种新型的LSI掩模图案规则检测系统。该系统的主要特点是所需的计算时间相对较小，即使对于非常大的电路(例如10,000个元件)，由于其功能灵活性，广泛应用于各种制造工艺，并且最大限度地减少了杂散误差。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A layout checking system for large scale integrated circuits

This paper describes a new design rule checking system for LSI mask patterns. Major features of the system are a relatively small computing time needed, even for very large circuits (e.g. 10,000 elements), wide applications to a variety of fabrication processes, due to its functional flexibility, and minimized spurious errors.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Papers on Twenty-five years of electronic design automation

自引率

0.00%

发文量

期刊最新文献

A comprehensive approach to a connectivity audit, or a fruitful comparison of apples and oranges LTX-A system for the directed automatic design of LSI circuits HAL: A multi-paradigm approach to automatic data path synthesis SLIC - symbolic layout of integrated circuits A new look at logic synthesis