{"title":"A new look at logic synthesis","authors":"J. Darringer, W. H. Jr. Joyner","doi":"10.1145/62882.62946","DOIUrl":"https://doi.org/10.1145/62882.62946","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116098012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Papers on Twenty-five years of electronic design automation","authors":"A. Newton","doi":"10.1145/62882","DOIUrl":"https://doi.org/10.1145/62882","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130107475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SUMMARY The purpose of this paper is to introduce a symbolic layout technique for MOS integrated circuits. We will give a description of symbolic layout, talk about its potential and briefly describe the symbolic layout system we have developed at AMI.
{"title":"SLIC - symbolic layout of integrated circuits","authors":"D. Gibson, S. Nance","doi":"10.1145/62882.62893","DOIUrl":"https://doi.org/10.1145/62882.62893","url":null,"abstract":"SUMMARY The purpose of this paper is to introduce a symbolic layout technique for MOS integrated circuits. We will give a description of symbolic layout, talk about its potential and briefly describe the symbolic layout system we have developed at AMI.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115278323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.
{"title":"Optimal layout of CMOS functional arrays","authors":"T. Uehara, W. Vancleemput","doi":"10.1145/62882.62902","DOIUrl":"https://doi.org/10.1145/62882.62902","url":null,"abstract":"Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121155195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Global wiring on a wire routing machine","authors":"R. Nair, S. Hong, Sandy Liles, R. Villani","doi":"10.1145/62882.62911","DOIUrl":"https://doi.org/10.1145/62882.62911","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"367 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123816914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kenji Yoshida, T. Mitsuhashi, Y. Nakada, Toshiaki Chiba, Kiyoshi Ogita, S. Nakatsuka
This paper describes a new design rule checking system for LSI mask patterns. Major features of the system are a relatively small computing time needed, even for very large circuits (e.g. 10,000 elements), wide applications to a variety of fabrication processes, due to its functional flexibility, and minimized spurious errors.
{"title":"A layout checking system for large scale integrated circuits","authors":"Kenji Yoshida, T. Mitsuhashi, Y. Nakada, Toshiaki Chiba, Kiyoshi Ogita, S. Nakatsuka","doi":"10.1145/62882.62899","DOIUrl":"https://doi.org/10.1145/62882.62899","url":null,"abstract":"This paper describes a new design rule checking system for LSI mask patterns. Major features of the system are a relatively small computing time needed, even for very large circuits (e.g. 10,000 elements), wide applications to a variety of fabrication processes, due to its functional flexibility, and minimized spurious errors.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128708512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"RELAX: A new circuit simulator for large scale MOS integrated circuits","authors":"E. Lelarasmee, A. Sangiovanni-Vincentelli","doi":"10.1145/62882.62937","DOIUrl":"https://doi.org/10.1145/62882.62937","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"67 22","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120886771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The problem of generating tests for sequential logic networks has become severe with large-scale integration (LSI). Since the internal gates cannot be tested by direct measurements, it is imperative that a rigorous logic test be developed to ensure quality at the chip level. The sequential complexity of many LSI chips exceeds the practical limitations of the familiar technique of modeling sequential logic for the application of combinational logic test-generation algorithms. Although other approaches, such as pseudo-random pattern generation, have been tried with some success, the pattern count may be quite large. This paper describes a method of test pattern generation that was developed with three objectives: to generate long pattern sequences systematically when needed, to model the sequential logic accurately so that any test generated would be valid, and to focus on assumed faults such as stuck 1 and stuck 0. Also discussed are the strengths and limitations of this method and some comparative results.
{"title":"Simulator-oriented fault test generator","authors":"T. Snethen","doi":"10.1145/62882.62922","DOIUrl":"https://doi.org/10.1145/62882.62922","url":null,"abstract":"The problem of generating tests for sequential logic networks has become severe with large-scale integration (LSI). Since the internal gates cannot be tested by direct measurements, it is imperative that a rigorous logic test be developed to ensure quality at the chip level. The sequential complexity of many LSI chips exceeds the practical limitations of the familiar technique of modeling sequential logic for the application of combinational logic test-generation algorithms. Although other approaches, such as pseudo-random pattern generation, have been tried with some success, the pattern count may be quite large. This paper describes a method of test pattern generation that was developed with three objectives: to generate long pattern sequences systematically when needed, to model the sequential logic accurately so that any test generated would be valid, and to focus on assumed faults such as stuck 1 and stuck 0. Also discussed are the strengths and limitations of this method and some comparative results.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127903019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The techniques to be described in this paper are generally applicable to any time domain, parallel fault, digital logic simulation system. The particular implementation was done on the CC-TEGAS3 system and quoted results are from this system. The first technique to be considered provides accuracy of fault simulation when using assignable nominal delays for different element types. The second technique provides for handling fault induced activity in a network, in such a way as to considerably reduce the amount of simulation time required.
{"title":"Timing analysis for digital fault simulation using assignable delays","authors":"E. Thompson, S. Szygenda, N. Billawala, R. Pierce","doi":"10.1145/62882.62919","DOIUrl":"https://doi.org/10.1145/62882.62919","url":null,"abstract":"The techniques to be described in this paper are generally applicable to any time domain, parallel fault, digital logic simulation system. The particular implementation was done on the CC-TEGAS3 system and quoted results are from this system.\u0000 The first technique to be considered provides accuracy of fault simulation when using assignable nominal delays for different element types. The second technique provides for handling fault induced activity in a network, in such a way as to considerably reduce the amount of simulation time required.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116986969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An experimental program is described for computing the d-c and transient response of transistor switching circuits of arbitrary configuration and size (up to 20 transistors) using the IBM 704 computer. One important feature of the program which is discussed is its ability to compile all the necessary equations automatically from input data describing the circuit parameters and configuration. Another is the solution of the transient problem by numerical integration OS the differential equations for the linear part of the circuit separately from those describing the transistors , the output from each set of equations being used periodically as input for the other set. Con-sidcrable increase in speed of integration is obtained in this manner, The method of d-c analysis is based on a topological-matrix formulation of the linear part of the problem. and its solution by Kron's method, followed by an iterative procedure for satisfying certain nonlinear side conditions imposed by the transintors. Although the transient analysis also uses a matrix formulation of the required differential equations, it is not based on a topological approach. However, a generalized topological-matrix formulation of the transient problem is given in an appendix. The nature of a serious theoretical limit on the rate of integration of the network equations. is discussed since it constitutes the principal computational barrier to a rapid solution of the transient problem. An outline of the tnore important programming procedures involved in the topological-matrix formulation is also given. Certain shortcomings of the program, and pitfalls to be avoided are pointed out. In particular , the importance of being able to modify or replace the transistor equivalent circuit (network model) is emphasized. Finally, the computed responses of a four-transistor switching circuit are displayed and shown to agree well with the observed responses, Int reduction This paper is based on the experience gained in writing an experiental program for analyzing transistor switching circuits using the IBM 704 computer. Thin program, called TAP for " transistor analysis program " , 102 was developed to provide circuit-design engineers with the ability to carry out " computational experiments " to aid in understanding, as well as designing, switching circuits. Although this objective was reached, the program has become obsolete because it was restricted to the analyeis of circuits containing a certain type of diffused base transistor which is of limited interest. Consequently, the program is not being maintained nor is it being made available for …
{"title":"D-C and transient analysis of networks using a digital computer","authors":"F. H. Branin, Development","doi":"10.1145/62882.62916","DOIUrl":"https://doi.org/10.1145/62882.62916","url":null,"abstract":"An experimental program is described for computing the d-c and transient response of transistor switching circuits of arbitrary configuration and size (up to 20 transistors) using the IBM 704 computer. One important feature of the program which is discussed is its ability to compile all the necessary equations automatically from input data describing the circuit parameters and configuration. Another is the solution of the transient problem by numerical integration OS the differential equations for the linear part of the circuit separately from those describing the transistors , the output from each set of equations being used periodically as input for the other set. Con-sidcrable increase in speed of integration is obtained in this manner, The method of d-c analysis is based on a topological-matrix formulation of the linear part of the problem. and its solution by Kron's method, followed by an iterative procedure for satisfying certain nonlinear side conditions imposed by the transintors. Although the transient analysis also uses a matrix formulation of the required differential equations, it is not based on a topological approach. However, a generalized topological-matrix formulation of the transient problem is given in an appendix. The nature of a serious theoretical limit on the rate of integration of the network equations. is discussed since it constitutes the principal computational barrier to a rapid solution of the transient problem. An outline of the tnore important programming procedures involved in the topological-matrix formulation is also given. Certain shortcomings of the program, and pitfalls to be avoided are pointed out. In particular , the importance of being able to modify or replace the transistor equivalent circuit (network model) is emphasized. Finally, the computed responses of a four-transistor switching circuit are displayed and shown to agree well with the observed responses, Int reduction This paper is based on the experience gained in writing an experiental program for analyzing transistor switching circuits using the IBM 704 computer. Thin program, called TAP for \" transistor analysis program \" , 102 was developed to provide circuit-design engineers with the ability to carry out \" computational experiments \" to aid in understanding, as well as designing, switching circuits. Although this objective was reached, the program has become obsolete because it was restricted to the analyeis of circuits containing a certain type of diffused base transistor which is of limited interest. Consequently, the program is not being maintained nor is it being made available for …","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117224661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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