基于分离设计配置的非自适应稀疏恢复和故障规避(仅摘要)

Ahmad Alzahrani, R. Demara
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引用次数: 5

摘要

提出了一种基于显式非自适应组测试(NGT)的可重构设备运行时故障诊断与规避方案。NGT涉及将可重构资源的不相交子集分组到测试池或样本中。每个测试池实现一个DC (Diagnostic Configuration),在诊断过程中进行功能测试。测试每个诊断池后的集体测试结果可以有效解码,以识别多达d个有缺陷的逻辑资源。利用统计文献中众所周知的d-分离性,导出了一种在设计时以最优最小测试组数构建NGT采样程序和资源放置的算法。所得到的DC的组合特性还保证了小于或等于d的任何可能的缺陷资源集不被至少一个DC利用,从而允许低开销的故障解决。它还提供了评估资源故障状态的能力。因此,所提出的测试方案避免了之前提出的自适应组测试对可重构硬件施加的时间密集型运行时诊断,而不影响诊断覆盖率。此外,本文提出的NGT方案还可以与其他容错方法相结合,改进其故障恢复策略。在Virtex-5 FPGA上使用Xilinx ISE Design Suite进行的一组MCNC基准测试的实验结果表明,在d=1和d=2时,片级的d可诊断性分别为99.15%和97.76%。
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Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only)
A run-time fault diagnosis and evasion scheme for reconfigurable devices is developed based on an explicit Non-adaptive Group Testing (NGT). NGT involves grouping disjunct subsets of reconfigurable resources into test pools, or samples. Each test pool realizes a Diagnostic Configuration (DC) performing functional testing during diagnosis procedure. The collective test outcomes after testing each diagnostic pool can be efficiently decoded to identify up to d defective logic resources. An algorithm for constructing NGT sampling procedure and resource placement during design time with optimal minimal number of test groups is derived through the well-known in statistical literature d-disjunctness property. The combinatorial properties of resultant DCs also guarantee that any possible set of defective resources less than or equal to d are not utilized by at least one DC, allowing a low-overhead fault resolution. It also provides the ability to assess the resources state of failure. The proposed testing scheme thus avoids time-intensive run-time diagnosis imposed by previously proposed adaptive group testing for reconfigurable hardware without compromising diagnostic coverage. In addition, proposed NGT scheme can be combined with other fault tolerance approaches to ameliorate their fault recovery strategies. Experimental results for a set of MCNC benchmarks using Xilinx ISE Design Suite on a Virtex-5 FPGA have demonstrated d-diagnosability at slice level with average accuracy of 99.15% and 97.76% for d=1 and d=2, respectively.
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