Improved power estimation for behavioral and gate level designs

A technique is presented for accurately computing the power of digital circuits described by behavioral- and gate-level designs. Accurate power estimation for high-level designs provides early warning of potential power problems, supporting design flexibility and a reduction of time and cost. The technique uses a behavioral VHDL specification or gate-level netlist as input. For a variety of combinational benchmark circuits, assuming the zero-delay model and uncorrelated primary inputs, the approach has been tested and compared with the Berkeley SIS power estimator. The proposed technique has been implemented in a program called the Behavioral Level Activity and Power Estimator (BLAPE). Experimental results demonstrate a savings in time with an average error less than 1.00%.