实验级联细胞动态记忆

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586230

D. Stark, H. Watanabe, T. Furuyama

{"title":"实验级联细胞动态记忆","authors":"D. Stark, H. Watanabe, T. Furuyama","doi":"10.1109/VLSIC.1994.586230","DOIUrl":null,"url":null,"abstract":"Series connected storage cells provide greater storage density for a given DRAM technology. We introduce several new features to exploit this advantage: an extra wordline to allow read and restore of the serial bits in the same order, a shift register row decoder with variable size redundancy, and a sense amp exchange configuration to ameliorate inter-bitline noise, We have designed and fabricated an experimental 32M DRAM that shows these ideas are feasible.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Experimental Cascade Cell Dynamic Memory\",\"authors\":\"D. Stark, H. Watanabe, T. Furuyama\",\"doi\":\"10.1109/VLSIC.1994.586230\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Series connected storage cells provide greater storage density for a given DRAM technology. We introduce several new features to exploit this advantage: an extra wordline to allow read and restore of the serial bits in the same order, a shift register row decoder with variable size redundancy, and a sense amp exchange configuration to ameliorate inter-bitline noise, We have designed and fabricated an experimental 32M DRAM that shows these ideas are feasible.\",\"PeriodicalId\":350730,\"journal\":{\"name\":\"Proceedings of 1994 IEEE Symposium on VLSI Circuits\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1994.586230\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1994.586230","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

串联连接的存储单元为给定的DRAM技术提供更大的存储密度。我们引入了几个新特性来利用这一优势:一个额外的字行，允许以相同的顺序读取和恢复串行位，一个具有可变大小冗余的移位寄存器行解码器，以及一个感测放大器交换配置，以改善位行间噪声。我们设计并制造了一个实验性的32M DRAM，表明这些想法是可行的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

An Experimental Cascade Cell Dynamic Memory

Series connected storage cells provide greater storage density for a given DRAM technology. We introduce several new features to exploit this advantage: an extra wordline to allow read and restore of the serial bits in the same order, a shift register row decoder with variable size redundancy, and a sense amp exchange configuration to ameliorate inter-bitline noise, We have designed and fabricated an experimental 32M DRAM that shows these ideas are feasible.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of 1994 IEEE Symposium on VLSI Circuits

自引率

0.00%

发文量