{"title":"用于课堂教学的VLSI微处理器设计","authors":"J. E. Varrientos, A. Rys","doi":"10.1109/UGIM.1991.148124","DOIUrl":null,"url":null,"abstract":"An outline for the instruction of VLSI microprocessor design is given. Considerable preplanning and complexity reduction by use of hierarchy is proposed to simplify the design procedure and reduce or eliminate design iterations late in the design. The microprocessor designed is a modified version of a simple-instruction accumulator machine designed for teaching software and hardware concepts. The design beings with the construction of standard cell libraries using the CAD tools VIVID and MAGIC. A design in VIVID is supported to verify circuit functionality, and a design in MAGIC is supported for final layout. The design continues with considerations for arithmetic-logic-unit (ALU) design, clocking schemes, bus-pre-charging, floorplanning, system timing, and interfacing to memory.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"VLSI microprocessor design for classroom instruction\",\"authors\":\"J. E. Varrientos, A. Rys\",\"doi\":\"10.1109/UGIM.1991.148124\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An outline for the instruction of VLSI microprocessor design is given. Considerable preplanning and complexity reduction by use of hierarchy is proposed to simplify the design procedure and reduce or eliminate design iterations late in the design. The microprocessor designed is a modified version of a simple-instruction accumulator machine designed for teaching software and hardware concepts. The design beings with the construction of standard cell libraries using the CAD tools VIVID and MAGIC. A design in VIVID is supported to verify circuit functionality, and a design in MAGIC is supported for final layout. The design continues with considerations for arithmetic-logic-unit (ALU) design, clocking schemes, bus-pre-charging, floorplanning, system timing, and interfacing to memory.<<ETX>>\",\"PeriodicalId\":163406,\"journal\":{\"name\":\"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/UGIM.1991.148124\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/UGIM.1991.148124","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
VLSI microprocessor design for classroom instruction
An outline for the instruction of VLSI microprocessor design is given. Considerable preplanning and complexity reduction by use of hierarchy is proposed to simplify the design procedure and reduce or eliminate design iterations late in the design. The microprocessor designed is a modified version of a simple-instruction accumulator machine designed for teaching software and hardware concepts. The design beings with the construction of standard cell libraries using the CAD tools VIVID and MAGIC. A design in VIVID is supported to verify circuit functionality, and a design in MAGIC is supported for final layout. The design continues with considerations for arithmetic-logic-unit (ALU) design, clocking schemes, bus-pre-charging, floorplanning, system timing, and interfacing to memory.<>
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