考虑容性负载的时钟缓冲极性分配

Jianchao Lu, B. Taskin
{"title":"考虑容性负载的时钟缓冲极性分配","authors":"Jianchao Lu, B. Taskin","doi":"10.1109/ISQED.2010.5450493","DOIUrl":null,"url":null,"abstract":"A clock buffer polarity assignment method is proposed that considers the impact of capacitive load on the peak current. It is shown that the peak current on the supply rails of a buffer is a monotonically increasing function of its driving capacitance. Consequently, the polarity of a clock buffer is assigned based on its capacitive load. The proposed method can be applied to assign buffer polarity on any number of levels of the clock tree. In experiments, the peak current on the clock tree in each local area is reduced by 36.3% on average. The worse case peak current of all the local areas are reduced by 35.7% on average. The proposed method is implemented with a pseudo-polynomial dynamic programming scheme demonstrating runtimes under a minute.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Clock buffer polarity assignment considering capacitive load\",\"authors\":\"Jianchao Lu, B. Taskin\",\"doi\":\"10.1109/ISQED.2010.5450493\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A clock buffer polarity assignment method is proposed that considers the impact of capacitive load on the peak current. It is shown that the peak current on the supply rails of a buffer is a monotonically increasing function of its driving capacitance. Consequently, the polarity of a clock buffer is assigned based on its capacitive load. The proposed method can be applied to assign buffer polarity on any number of levels of the clock tree. In experiments, the peak current on the clock tree in each local area is reduced by 36.3% on average. The worse case peak current of all the local areas are reduced by 35.7% on average. The proposed method is implemented with a pseudo-polynomial dynamic programming scheme demonstrating runtimes under a minute.\",\"PeriodicalId\":369046,\"journal\":{\"name\":\"2010 11th International Symposium on Quality Electronic Design (ISQED)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 11th International Symposium on Quality Electronic Design (ISQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2010.5450493\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 11th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2010.5450493","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15

摘要

提出了一种考虑电容性负载对峰值电流影响的时钟缓冲极性分配方法。结果表明,缓冲器供电轨道上的峰值电流是其驱动电容的单调递增函数。因此,时钟缓冲器的极性是根据其容性负载分配的。所提出的方法可以应用于在时钟树的任意级别上分配缓冲极性。在实验中,时钟树各局部区域的峰值电流平均降低了36.3%。最坏情况下各区域峰值电流平均降低35.7%。该方法采用伪多项式动态规划方案实现,运行时间小于1分钟。
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Clock buffer polarity assignment considering capacitive load
A clock buffer polarity assignment method is proposed that considers the impact of capacitive load on the peak current. It is shown that the peak current on the supply rails of a buffer is a monotonically increasing function of its driving capacitance. Consequently, the polarity of a clock buffer is assigned based on its capacitive load. The proposed method can be applied to assign buffer polarity on any number of levels of the clock tree. In experiments, the peak current on the clock tree in each local area is reduced by 36.3% on average. The worse case peak current of all the local areas are reduced by 35.7% on average. The proposed method is implemented with a pseudo-polynomial dynamic programming scheme demonstrating runtimes under a minute.
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