采用行、列旁路的低功耗乘法器设计

2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI:10.1109/SOCCON.2009.5398054

Jin-Tai Yan, Zhi-Wei Chen

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引用次数: 59

摘要

在简化阵列乘法器中增量加法器和半加法器而不是全加法器的基础上，提出了一种行、列旁路的低功耗乘法器设计。与20个测试示例的行旁通乘法器、列旁通乘法器和二维旁通乘法器相比，实验结果表明，对于4×4、8×8和16×16乘法器，我们提出的乘法器平均降低了25.7%的功耗，硬件开销仅为15%。

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Low-power multiplier design with row and column bypassing

Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multipliers and the 2-dimensional bypass multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% of the power dissipation with only 15% hardware overhead on the average for 4×4, 8×8 and 16×16 multipliers.

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2009 IEEE International SOC Conference (SOCC)

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