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引用次数: 24
摘要
我们提出了一个10位1-MS/s连续近似模数转换器核心，包括电荷再分配数模转换器和比较器。一种新的线性校准技术可以使用受kT/C噪声限制的几乎最小的电容器。无数字模块的ADC核心已在0.18 μ m CMOS工艺中制造，在1.8 V电源下消耗110muW。经过标定，SNDR提高9.0 db, SFDR提高23.3dB。测量的SNDR和SFDR分别为51.1 dB和69.8 dB。
A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS
We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital blocks has been fabricated in a 0.18-mum CMOS process and consumes 110muW at 1.8 V power supply. With the calibration it achieves 9.0-dB improvement of SNDR and 23.3dB improvement of SFDR. The measured SNDR and SFDR are 51.1 dB and 69.8 dB respectively.
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