{"title":"功率平面噪声耦合到高速信号","authors":"F. Demuynck, L. Eichinger, V. Poisson","doi":"10.1109/SAPIW.2015.7237390","DOIUrl":null,"url":null,"abstract":"Power plane noise is a well-known source of signal integrity (SI) issues in a high speed digital design. This paper first reviews the basic principles which are at the root of the problem. We then illustrate how electronic design automation (EDA) tools can be used to analyze the phenomenon and provide guidance on how to mitigate the issue by adjusting the design.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Power plane noise coupling to high speed signals\",\"authors\":\"F. Demuynck, L. Eichinger, V. Poisson\",\"doi\":\"10.1109/SAPIW.2015.7237390\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Power plane noise is a well-known source of signal integrity (SI) issues in a high speed digital design. This paper first reviews the basic principles which are at the root of the problem. We then illustrate how electronic design automation (EDA) tools can be used to analyze the phenomenon and provide guidance on how to mitigate the issue by adjusting the design.\",\"PeriodicalId\":231437,\"journal\":{\"name\":\"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SAPIW.2015.7237390\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAPIW.2015.7237390","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Power plane noise is a well-known source of signal integrity (SI) issues in a high speed digital design. This paper first reviews the basic principles which are at the root of the problem. We then illustrate how electronic design automation (EDA) tools can be used to analyze the phenomenon and provide guidance on how to mitigate the issue by adjusting the design.
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