Y. Yu, S. Choi, Dong-Yong Kim, KyuTae Park, H. Ahn
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Design of CMOS composite transistors with improved operating region
Proposes two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistors 1 and 2 employ a p-type folded composite transistor and an electronic Zener diode in order to decrease the threshold voltage, respectively. The simulation has been carried out using 0.25/spl mu/m n-well process with 2.5V supply voltage.
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