{"title":"用于45纳米以下技术的高性能节能存储电路技术","authors":"A. Agarwal, R. Krishnamurthy","doi":"10.1109/SOCC.2006.283907","DOIUrl":null,"url":null,"abstract":"This tutorial discusses challenges and design solutions for high-performance energy efficient memory/register file circuit design. Technology scaling trends for leakage and process variation for sub-45nm technologies are analyzed, with special emphasis on their impact on wide fan in OR gates found in high performance register file. Novel high-speed and leakage/process tolerant circuits are reviewed. Leakage/process sensors which enable these processes compensating techniques are presented.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High-performance energy-efficient memory circuit technologies for sub-45nm technologies\",\"authors\":\"A. Agarwal, R. Krishnamurthy\",\"doi\":\"10.1109/SOCC.2006.283907\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This tutorial discusses challenges and design solutions for high-performance energy efficient memory/register file circuit design. Technology scaling trends for leakage and process variation for sub-45nm technologies are analyzed, with special emphasis on their impact on wide fan in OR gates found in high performance register file. Novel high-speed and leakage/process tolerant circuits are reviewed. Leakage/process sensors which enable these processes compensating techniques are presented.\",\"PeriodicalId\":345714,\"journal\":{\"name\":\"2006 IEEE International SOC Conference\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2006.283907\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2006.283907","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-performance energy-efficient memory circuit technologies for sub-45nm technologies
This tutorial discusses challenges and design solutions for high-performance energy efficient memory/register file circuit design. Technology scaling trends for leakage and process variation for sub-45nm technologies are analyzed, with special emphasis on their impact on wide fan in OR gates found in high performance register file. Novel high-speed and leakage/process tolerant circuits are reviewed. Leakage/process sensors which enable these processes compensating techniques are presented.
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