Technology assessment for MRAM cells with magnet/semiconductor bits

Although MRAM circuits can be fabricated without the need for an integrated semiconductor switch in each bit, most applications will require a DRAM-like floorplan with combined magnetlsemiconductor bits. In a first approach to assess the feasibility of such integration, we have integrated spin-valve structures with semiconductor diodes [I]. Further, in an [MEC I INESC collaboration (ESPRIT #28.229 I TI-MRAM) the integration feasibility of tunnel junctions is assessed. The main issues we are tackling are the fabrication of arrays of magnetic tunneljunction I semiconductor elements and the MTI performance as a function of the parameters of the integration pmcess. In this paper we present results of our assessment of MRAM circuits with magnetlsemiconductor bits.