{"title":"高效e类开关模式功率放大器的随机搜索算法设计与优化","authors":"M. M. Tabrizi, N. Masoumi","doi":"10.1109/ICM.2004.1434268","DOIUrl":null,"url":null,"abstract":"The class E switched mode power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. Main three parts of the power amplifier that specify its total efficiency are: the Q factor of output band-pass filter, the transistor on-state resistance, and the driver stage. In this paper, we design and optimize three common structures of power amplifiers using a random search algorithm. Optimized designs are simulated with HSPICE in 0.25 /spl mu/m CMOS technology at the carrier frequency of 5.2 GHz. The maximum efficiency for each structure is calculated, and then its bottle-neck is determined. We also achieve the total efficiency of 92.3% for the power amplifier.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"High efficiency class-E switched mode power amplifier design and optimization with random search algorithm\",\"authors\":\"M. M. Tabrizi, N. Masoumi\",\"doi\":\"10.1109/ICM.2004.1434268\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The class E switched mode power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. Main three parts of the power amplifier that specify its total efficiency are: the Q factor of output band-pass filter, the transistor on-state resistance, and the driver stage. In this paper, we design and optimize three common structures of power amplifiers using a random search algorithm. Optimized designs are simulated with HSPICE in 0.25 /spl mu/m CMOS technology at the carrier frequency of 5.2 GHz. The maximum efficiency for each structure is calculated, and then its bottle-neck is determined. We also achieve the total efficiency of 92.3% for the power amplifier.\",\"PeriodicalId\":359193,\"journal\":{\"name\":\"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2004.1434268\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2004.1434268","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
E类开关模式功率放大器由负载网络和单个晶体管组成,该晶体管在输出信号的载波频率上作为开关工作。决定功率放大器总效率的主要有三个部分:输出带通滤波器的Q因子、晶体管导通电阻和驱动级。本文采用随机搜索算法对三种常见的功率放大器结构进行了设计和优化。在载波频率为5.2 GHz的0.25 /spl μ m CMOS技术下,利用HSPICE对优化设计进行了仿真。计算每种结构的最大效率,然后确定其瓶颈。我们还实现了功率放大器的总效率为92.3%。
High efficiency class-E switched mode power amplifier design and optimization with random search algorithm
The class E switched mode power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. Main three parts of the power amplifier that specify its total efficiency are: the Q factor of output band-pass filter, the transistor on-state resistance, and the driver stage. In this paper, we design and optimize three common structures of power amplifiers using a random search algorithm. Optimized designs are simulated with HSPICE in 0.25 /spl mu/m CMOS technology at the carrier frequency of 5.2 GHz. The maximum efficiency for each structure is calculated, and then its bottle-neck is determined. We also achieve the total efficiency of 92.3% for the power amplifier.