{"title":"用于Wi-Fi 11ac直接转换接收器的模式可配置模拟基带,利用单个滤波ΔΣ ADC","authors":"Chi-Yun Wang, Shu-Wei Chu, Tzu-Hsuin Peng, Jen-Che Tsai, Chih-Hong Lou","doi":"10.1109/RFIC.2016.7508278","DOIUrl":null,"url":null,"abstract":"A mode-configurable filtering ΔΣ ADC is utilized as the analog baseband in a Wi-Fi 11ac direct-conversion receiver (RX). The filtering ΔΣ ADC providing both 2nd-order out-of-band filtering and 3rd-order in-band noise shaping is realized with only two opamps. A SAR-quantizer with built-in discrete-time (DT) excess-loop delay (ELD) compensation technique is also adopted. The filtering ΔΣ ADC is clocked at 480 MHz or 960 MHz and achieves 77-to-58 dB dynamic range (DR) in 10 MHz - 80 MHz bandwidth. With the aid of the filtering ability, the interferer DR at 4× bandwidth is at least 71.3 dB over modes. This work is fabricated in 28-nm low-power (LP) technology with 0.06 mm2 of active area. It consumes 3.97 mW or 6.39 mW over different clock rates, resulting a highest Schreier's FoM of 171 dB (BW20) and a best 4×-bandwidth Walden's FoM [2] of 13.3 fJ/c (BW160) among all modes.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A mode-configurable analog baseband for Wi-Fi 11ac direct-conversion receiver utilizing a single filtering ΔΣ ADC\",\"authors\":\"Chi-Yun Wang, Shu-Wei Chu, Tzu-Hsuin Peng, Jen-Che Tsai, Chih-Hong Lou\",\"doi\":\"10.1109/RFIC.2016.7508278\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A mode-configurable filtering ΔΣ ADC is utilized as the analog baseband in a Wi-Fi 11ac direct-conversion receiver (RX). The filtering ΔΣ ADC providing both 2nd-order out-of-band filtering and 3rd-order in-band noise shaping is realized with only two opamps. A SAR-quantizer with built-in discrete-time (DT) excess-loop delay (ELD) compensation technique is also adopted. The filtering ΔΣ ADC is clocked at 480 MHz or 960 MHz and achieves 77-to-58 dB dynamic range (DR) in 10 MHz - 80 MHz bandwidth. With the aid of the filtering ability, the interferer DR at 4× bandwidth is at least 71.3 dB over modes. This work is fabricated in 28-nm low-power (LP) technology with 0.06 mm2 of active area. It consumes 3.97 mW or 6.39 mW over different clock rates, resulting a highest Schreier's FoM of 171 dB (BW20) and a best 4×-bandwidth Walden's FoM [2] of 13.3 fJ/c (BW160) among all modes.\",\"PeriodicalId\":163595,\"journal\":{\"name\":\"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"2012 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2016.7508278\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2016.7508278","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A mode-configurable analog baseband for Wi-Fi 11ac direct-conversion receiver utilizing a single filtering ΔΣ ADC
A mode-configurable filtering ΔΣ ADC is utilized as the analog baseband in a Wi-Fi 11ac direct-conversion receiver (RX). The filtering ΔΣ ADC providing both 2nd-order out-of-band filtering and 3rd-order in-band noise shaping is realized with only two opamps. A SAR-quantizer with built-in discrete-time (DT) excess-loop delay (ELD) compensation technique is also adopted. The filtering ΔΣ ADC is clocked at 480 MHz or 960 MHz and achieves 77-to-58 dB dynamic range (DR) in 10 MHz - 80 MHz bandwidth. With the aid of the filtering ability, the interferer DR at 4× bandwidth is at least 71.3 dB over modes. This work is fabricated in 28-nm low-power (LP) technology with 0.06 mm2 of active area. It consumes 3.97 mW or 6.39 mW over different clock rates, resulting a highest Schreier's FoM of 171 dB (BW20) and a best 4×-bandwidth Walden's FoM [2] of 13.3 fJ/c (BW160) among all modes.