基于FPGA的模糊逻辑可控环滤波器的DPLL

M. Moradi, M. Ehsanian
{"title":"基于FPGA的模糊逻辑可控环滤波器的DPLL","authors":"M. Moradi, M. Ehsanian","doi":"10.1109/ICM.2017.8268812","DOIUrl":null,"url":null,"abstract":"Carrier recovery is very essential in tracking systems especially in noisy environment and high dynamic receivers. There are different PLL approaches that are proposed for making compromise between noise and dynamic in literatures. Here, a novel Digital PLL is proposed with a type-2 fuzzy logic controller for improving compatibility with noise and user dynamic in digital receivers. Adjusting filter coefficients with a type-2 Fuzzy Logic controller will result in best operation for rejecting noise and dynamic compensation. The proposed DPLL resultant by Xilinx System Generator shows better response to phase step, input signal jitter, frequency step and ramp signals.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An FPGA based DPLL with fuzzy logic controllable loop filters\",\"authors\":\"M. Moradi, M. Ehsanian\",\"doi\":\"10.1109/ICM.2017.8268812\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Carrier recovery is very essential in tracking systems especially in noisy environment and high dynamic receivers. There are different PLL approaches that are proposed for making compromise between noise and dynamic in literatures. Here, a novel Digital PLL is proposed with a type-2 fuzzy logic controller for improving compatibility with noise and user dynamic in digital receivers. Adjusting filter coefficients with a type-2 Fuzzy Logic controller will result in best operation for rejecting noise and dynamic compensation. The proposed DPLL resultant by Xilinx System Generator shows better response to phase step, input signal jitter, frequency step and ramp signals.\",\"PeriodicalId\":115975,\"journal\":{\"name\":\"2017 29th International Conference on Microelectronics (ICM)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 29th International Conference on Microelectronics (ICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2017.8268812\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2017.8268812","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

在跟踪系统中,特别是在噪声环境和高动态接收机中,载波恢复是非常重要的。为了在噪声和动态之间取得折衷,文献中提出了不同的锁相环方法。为了提高数字接收机对噪声和用户动态的兼容性,提出了一种带有2型模糊控制器的新型数字锁相环。采用2型模糊控制器调节滤波器系数,可达到抑制噪声和动态补偿的最佳运行效果。Xilinx系统发生器生成的DPLL对相位阶跃、输入信号抖动、频率阶跃和斜坡信号都有较好的响应。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
An FPGA based DPLL with fuzzy logic controllable loop filters
Carrier recovery is very essential in tracking systems especially in noisy environment and high dynamic receivers. There are different PLL approaches that are proposed for making compromise between noise and dynamic in literatures. Here, a novel Digital PLL is proposed with a type-2 fuzzy logic controller for improving compatibility with noise and user dynamic in digital receivers. Adjusting filter coefficients with a type-2 Fuzzy Logic controller will result in best operation for rejecting noise and dynamic compensation. The proposed DPLL resultant by Xilinx System Generator shows better response to phase step, input signal jitter, frequency step and ramp signals.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
OFDM signal up and down frequency conversions by a sampling method using a SOA-MZI A solution for channel electron migration in normally-off MIS-HEMT with buried fluorine ions Physical parameter adjustment for a power over fiber device with a self-developed numerical model of optical propagation in the seafloor observatory context Thermal drift compensation of piezoresistive implantable blood pressure sensors with low cost analog solutions Synthesis of a fractional order audio boost filter
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1