具有数据相关抖动测量的4Gb/s自适应FFE/DFE接收机

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI:10.1109/ESSCIRC.2011.6044979

Tae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang

{"title":"具有数据相关抖动测量的4Gb/s自适应FFE/DFE接收机","authors":"Tae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang","doi":"10.1109/ESSCIRC.2011.6044979","DOIUrl":null,"url":null,"abstract":"This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm × 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement\",\"authors\":\"Tae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang\",\"doi\":\"10.1109/ESSCIRC.2011.6044979\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm × 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.\",\"PeriodicalId\":239979,\"journal\":{\"name\":\"2011 Proceedings of the ESSCIRC (ESSCIRC)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Proceedings of the ESSCIRC (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2011.6044979\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2011.6044979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

提出了一种基于数据相关抖动测量算法的自适应FFE/DFE接收机。提出的自适应算法通过测量输入数据相关的抖动来确定补偿水平。该自适应算法与CDR鉴相器相结合。该接收机采用0.13 μm CMOS工艺制作，在2GHz时均衡补偿范围高达26 dB。测试芯片验证了40英寸FR4走线和53厘米FPC(柔性印刷电路)通道。接收机尺寸为440μm × 520μm, 1.2 v供电，功耗为49mW(不含I/O缓冲)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement

This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm × 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2011 Proceedings of the ESSCIRC (ESSCIRC)

自引率

0.00%

发文量