An area-optimized implementation for AES with hybrid countermeasures against power analysis

Since its adoption as a new encryption standard by NIST, the Advanced Encryption Standard (AES) has become the default choice for various applications. On the other hand, a straightforward implementation of the AES is vulnerable to different forms of side channel attacks. In this paper, we explore several countermeasure techniques against power analysis attacks. In particular, we present an area optimized design that combines shuffling, as a hiding countermeasure, with some recently proposed masking techniques. The developed power analysis resistant AES-128 ECB encryption/decryption engine requires 3090 slices of a Xilinx Virtex-II xc2v1000-6-bg575 FPGA, runs at a maximum clock speed of 51.75 MHz and produces a throughput of up to 15.33 Mbps.