高效的3输入异或，适用于低压低功耗高速应用

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824054

Kuo-Hsing Cheng, Ven-Chieh Hsieh

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引用次数: 3

摘要

基于通型晶体管设计方法，提出了一种适用于低压、低压高速应用的新型三输入异或门。将现有的五种电路与新提出的栅极进行了比较。结果表明，与CPL结构和CMOS结构相比，新电路的功率延迟积至少提高了50%。此外，所提出的新电路也可以工作在低至1v。因此，所提出的新电路适用于低功耗、低电压和高速应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High efficient 3-input XOR for low-voltage low-power high-speed applications

A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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