50GBit/s PAM-4 Driver Circuit Based on Variable Gain Distributed Power Combiner

In this work an analog driver circuit for pulse amplitude modulated data signals with four amplitude levels (PAM-4) is investigated. The driver circuit is based on a distributed combining cell, which performs the PAM4 generation from binary input data streams. Due to the distributed topology, the driver core provides a high analog bandwidth and is well suited for high-speed operation. Since the amplification of both combiner paths can be adjusted individually, the combiner circuit offers predistortion capabilities when driving loads with a nonlinear transfer function. A one-stage prototype circuit using heterojunction bipolar transistors (HBTs) is implemented in a 130nm SiGe BiCMOS technology. Time-domain measurements prove PAM-4 signal generation at an output bitrate of 50GBit/s, while the driver consumes a DC power of 63mW. Additionally, predistortion of the circuit is demonstrated at 25GBit/s, leading to a variable vertical spacing of the amplitude levels.