Model Checking Verilog Descriptions of Cell Libraries

We present a formal semantics for a subset of Verilog, commonly used todescribe cell libraries, in terms of transition systems.Such transition systems can serve as input to symbolic model checking,for example equivalence checking with a transistor netlist description. Weimplement our formal semantics as an encoding from the subset of Verilog tothe input language of the SMV model-checker.Experiments show that this approach is able to verify complete cell libraries.