基于Booth重编码算法的2补数并行乘法器

Chandrashekhar T. Kukade, R. Deshmukh, R. Patrikar
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引用次数: 6

摘要

本文提出了一种利用改进的Booth对2的补码数进行编码的新型并行乘法器结构。基本的布斯重编码算法需要对乘法进行加法和移位操作,这些步骤使这个乘法器是顺序的。使用Booth的重新编码算法和简单的Brown加法器阵列可以实现并行乘法,但是需要更多的加法器才能得到正确的输出。其他并行乘法技术可以使用布斯的重新编码算法。然而,这些阵列乘法器还需要加、移和额外的控制单元。提出的设计有两个主要特点;第一是改进的产生部分产品的布斯重编码单元,第二是改进的加法器阵列。改进的加法器块阵列设计,比传统的布斯重编码乘法器使用更少的加法器。多路复用器是布斯编码单元的基本单元,合成采用180nm技术。所提出的设计比传统的布斯重新编码2的互补并行乘法器使用更少的功率。
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A Novel Parallel Multiplier for 2's Complement Numbers Using Booth's Recoding Algorithm
A novel architecture of parallel multiplier using modified Booth's recoding unit for 2's complement numbers is presented in this paper. The basic Booth's recoding algorithm requires add and shift operations for multiplication, these steps makes this multiplier sequential. Parallel multiplication can be achieved using Booth's recoding algorithm and simple Brown's array of adders, but it requires more number of adders to get correct output. Other parallel multiplication techniques are available using Booth's recoding algorithm. However, these array multiplier also requires add, shift and extra control unit. The proposed design has two major features; first is modified Booth's recoding unit which produces partial products second is modified array of adders. Modified array of adder block designed, which uses less number of adders than conventional Booth's recoding multiplier. Multiplexers are basic unit used for Booth's recoding unit and synthesis has been carried out using 180 nm technology. The proposed design uses less power than conventional Booth's recoding 2's complement parallel multiplier.
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