S. Zaychenko, Pavlo Leshtaev, B. Gureev, Maksym Shliakhtun
{"title":"结构CDC分析方法","authors":"S. Zaychenko, Pavlo Leshtaev, B. Gureev, Maksym Shliakhtun","doi":"10.1109/EWDTS.2016.7807671","DOIUrl":null,"url":null,"abstract":"This paper analyzes a problem of Clock Domain Crossings (CDC) verification in modern System-on-Chips. We suggest a set of topological methods that automatically discover CDCs and detect typical structural mistakes frequently occurring at the border of independent clock domains in many designs. Detecting structural design rule violations is a critical part of a complex CDC verification flow implemented in our commercial product ALINT-PRO-CDC™ [1].","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Structural CDC analysis methods\",\"authors\":\"S. Zaychenko, Pavlo Leshtaev, B. Gureev, Maksym Shliakhtun\",\"doi\":\"10.1109/EWDTS.2016.7807671\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper analyzes a problem of Clock Domain Crossings (CDC) verification in modern System-on-Chips. We suggest a set of topological methods that automatically discover CDCs and detect typical structural mistakes frequently occurring at the border of independent clock domains in many designs. Detecting structural design rule violations is a critical part of a complex CDC verification flow implemented in our commercial product ALINT-PRO-CDC™ [1].\",\"PeriodicalId\":364686,\"journal\":{\"name\":\"2016 IEEE East-West Design & Test Symposium (EWDTS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE East-West Design & Test Symposium (EWDTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2016.7807671\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2016.7807671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper analyzes a problem of Clock Domain Crossings (CDC) verification in modern System-on-Chips. We suggest a set of topological methods that automatically discover CDCs and detect typical structural mistakes frequently occurring at the border of independent clock domains in many designs. Detecting structural design rule violations is a critical part of a complex CDC verification flow implemented in our commercial product ALINT-PRO-CDC™ [1].