Design of a high-speed RF envelope detector with dynamic load and derivative superposition techniques

This paper presents a new high speed, high conversion gain envelope detector (ED) using dynamic load (DL) and 2nd order nonlinearity maximization techniques. To enhance the conversion gain and speed of conventional ED architectures, the proposed ED uses a dynamic load (DL) technique with class-AB architecture to increase the speed and tune the output impedance dynamically. To improve nonlinearity of the ED, derivative superposition (DS) is used. By biasing the NMOS and PMOS transistors of the ED initially in different regions of operation, 2nd order derivative of transconductance (g2) is maximized which increases the 2nd order conversion gain. This configuration enables low power consumption without compromising the conversion gain. Simulation results of the proposed ED in 0.18μm CMOS technology show a high data rate of 14.5Mbps with power consumption of 1.21μW.