静、动态特性分析。

S. Kato, Osamu Tomisawa, Y. Horiba, T. Nakano
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引用次数: 0

摘要

在比较了垂直注入逻辑结构与常规结构的电特性后,采用简化的一维模型分析了垂直注入逻辑结构的静力特性和动力特性,并进行了实验验证。分析表明,最小传输延迟时间由n-p-n晶体管的截止频率和从基底注入外延层的孔的有效寿命决定。v.i.l结构中的底部注入器减少了井眼的有效寿命,从而提高了最小传播延迟时间。此外,当截止频率较高时,由于有效寿命的减少而导致的最小传播延迟时间的改善更为明显。实验结果表明,与分析结果一致,vil的最小传播延迟时间提高了1.6倍。
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Analysis of static and dynamic characteristics in v.i.l.
After a survey of the electrical characteristics for vertical injection logic (v.i.l.) structure compared with the conventional i.i.l. structure, static characteristics and dynamic behaviour for the v.i.l. structure are analysed by using a simplified one-dimensional model, and experimental verifications are carried out. The analysis reveals that the minimum propagation delay time is determined by the cutoff frequency of the n-p-n transistor and the effective lifetime of holes injected into the epitaxial layer from the base. The bottom injector in the v.i.l. structure reduces the effective lifetime of the holes, which results in improved minimum propagation delay times. In addition, the improvement in the minimum propagation delay times due to a reduction in the effective lifetime is more pronounced when the cutoff frequency is higher. Experimental results show that the minimum propagation delay time for v.i.l. is improved by a factor of 1.6, as predicted from the analysis.
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