SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement

Except for regular arrays, yield enhancement for high performance VLSI systems is usually addressed at the physical layers rather than at the architectural level. In addition, pipelines are prevalent in many SoC architectures. In this paper we present new architectural approaches and results to improve the yield and yield/area of pipelines by using redundancy and steering logic . We present a procedure of time complexity O(n) that finds the minimal number of switches to insert within an n-stage redundant pipeline of order q to improve yield. Experimental results indicate that for parameter values of interests, this procedure also improves the yield/area of the pipeline, especially when the yields for some modules are low.