{"title":"无栅格遮阳的薄基晶体硅太阳能电池","authors":"D. Aiken, A. Barnett","doi":"10.1109/PVSC.1997.654201","DOIUrl":null,"url":null,"abstract":"Two major opportunities for increasing the performance of present day silicon solar cells involve reducing both the thickness and the grid shading. The ideal silicon photovoltaic device will be 20-100 /spl mu/m thick, will incorporate light trapping, and will not be shaded by contact metallization. Practicality also requires that these devices be supported by a low cost substrate. For the first time, a thin, substrate-based crystalline silicon solar cell has been designed and fabricated with no grid shading. Contacts are sandwiched between a supportive silicon substrate and a 40 /spl mu/m thick active silicon device layer. Device results include a 535 mV V/sub oc/, and negligible shunt conductance and series resistance.","PeriodicalId":251166,"journal":{"name":"Conference Record of the Twenty Sixth IEEE Photovoltaic Specialists Conference - 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Thin, substrate-based crystalline silicon solar cells with no grid shading\",\"authors\":\"D. Aiken, A. Barnett\",\"doi\":\"10.1109/PVSC.1997.654201\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Two major opportunities for increasing the performance of present day silicon solar cells involve reducing both the thickness and the grid shading. The ideal silicon photovoltaic device will be 20-100 /spl mu/m thick, will incorporate light trapping, and will not be shaded by contact metallization. Practicality also requires that these devices be supported by a low cost substrate. For the first time, a thin, substrate-based crystalline silicon solar cell has been designed and fabricated with no grid shading. Contacts are sandwiched between a supportive silicon substrate and a 40 /spl mu/m thick active silicon device layer. Device results include a 535 mV V/sub oc/, and negligible shunt conductance and series resistance.\",\"PeriodicalId\":251166,\"journal\":{\"name\":\"Conference Record of the Twenty Sixth IEEE Photovoltaic Specialists Conference - 1997\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of the Twenty Sixth IEEE Photovoltaic Specialists Conference - 1997\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PVSC.1997.654201\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the Twenty Sixth IEEE Photovoltaic Specialists Conference - 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PVSC.1997.654201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Thin, substrate-based crystalline silicon solar cells with no grid shading
Two major opportunities for increasing the performance of present day silicon solar cells involve reducing both the thickness and the grid shading. The ideal silicon photovoltaic device will be 20-100 /spl mu/m thick, will incorporate light trapping, and will not be shaded by contact metallization. Practicality also requires that these devices be supported by a low cost substrate. For the first time, a thin, substrate-based crystalline silicon solar cell has been designed and fabricated with no grid shading. Contacts are sandwiched between a supportive silicon substrate and a 40 /spl mu/m thick active silicon device layer. Device results include a 535 mV V/sub oc/, and negligible shunt conductance and series resistance.