Natalia A. Fernandez-Garcia, J. Albó-Canals, V. Brea, J. Riera-Babures, D. Cabello, X. Vilasís-Cardona
{"title":"CNN硬件缩减中Split&Shift技术的验证","authors":"Natalia A. Fernandez-Garcia, J. Albó-Canals, V. Brea, J. Riera-Babures, D. Cabello, X. Vilasís-Cardona","doi":"10.1109/ECCTD.2007.4529543","DOIUrl":null,"url":null,"abstract":"The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Verification of Split&Shift techniques for CNN hardware reduction\",\"authors\":\"Natalia A. Fernandez-Garcia, J. Albó-Canals, V. Brea, J. Riera-Babures, D. Cabello, X. Vilasís-Cardona\",\"doi\":\"10.1109/ECCTD.2007.4529543\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.\",\"PeriodicalId\":445822,\"journal\":{\"name\":\"2007 18th European Conference on Circuit Theory and Design\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 18th European Conference on Circuit Theory and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCTD.2007.4529543\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 18th European Conference on Circuit Theory and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2007.4529543","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Verification of Split&Shift techniques for CNN hardware reduction
The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.