{"title":"用于无线通信的高效MPSK解调器和相位恢复系统","authors":"M. Saber","doi":"10.1109/jec-ecc.2017.8305793","DOIUrl":null,"url":null,"abstract":"An efficient demodulator and phase recovery system for phase shift keying (M-PSK) modulation scheme in wireless receivers has been designed and implemented. Stability, accuracy, simple structure, low power consumption compared to conventional methods such as Costas loop, are the main features provided by the proposed system. Different simulations using the Matlab program indicate that, the proposed system decreases the phase estimation time, and lowers the bit error rate (BER) compared to conventional method. The proposed architecture implemented on a field programmable gate array (FPGA) board. The implementation results indicate, that the proposed system reduced the power consumption by 28%, and works at a clock frequency faster by 67%, compared to traditional Costas loop architecture.","PeriodicalId":406498,"journal":{"name":"2017 Japan-Africa Conference on Electronics, Communications and Computers (JAC-ECC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Efficient MPSK demodulator and phase recovery system for wireless communication\",\"authors\":\"M. Saber\",\"doi\":\"10.1109/jec-ecc.2017.8305793\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An efficient demodulator and phase recovery system for phase shift keying (M-PSK) modulation scheme in wireless receivers has been designed and implemented. Stability, accuracy, simple structure, low power consumption compared to conventional methods such as Costas loop, are the main features provided by the proposed system. Different simulations using the Matlab program indicate that, the proposed system decreases the phase estimation time, and lowers the bit error rate (BER) compared to conventional method. The proposed architecture implemented on a field programmable gate array (FPGA) board. The implementation results indicate, that the proposed system reduced the power consumption by 28%, and works at a clock frequency faster by 67%, compared to traditional Costas loop architecture.\",\"PeriodicalId\":406498,\"journal\":{\"name\":\"2017 Japan-Africa Conference on Electronics, Communications and Computers (JAC-ECC)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Japan-Africa Conference on Electronics, Communications and Computers (JAC-ECC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/jec-ecc.2017.8305793\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Japan-Africa Conference on Electronics, Communications and Computers (JAC-ECC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/jec-ecc.2017.8305793","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient MPSK demodulator and phase recovery system for wireless communication
An efficient demodulator and phase recovery system for phase shift keying (M-PSK) modulation scheme in wireless receivers has been designed and implemented. Stability, accuracy, simple structure, low power consumption compared to conventional methods such as Costas loop, are the main features provided by the proposed system. Different simulations using the Matlab program indicate that, the proposed system decreases the phase estimation time, and lowers the bit error rate (BER) compared to conventional method. The proposed architecture implemented on a field programmable gate array (FPGA) board. The implementation results indicate, that the proposed system reduced the power consumption by 28%, and works at a clock frequency faster by 67%, compared to traditional Costas loop architecture.