60 GHz single-chip 90nm CMOS radio with integrated signal processor

A 60GHz single-chip CMOS radio has been fully integrated using standard 90nm CMOS process technology. The digitally controlled wideband super-heterodyne architecture combined with a high-speed digital signal processor has been designed to support the whole 57 to 66 GHz bandwidth available, and enable data throughput exceeding 7Gbps QPSK and 15Gbps 16QAM for a total DC power budget below 200mW. The receiver chain provides a total gain of nearly 50dB for a total noise figure below 9dB while the power amplifier delivers +8.4dBm saturated output power at 60GHz. The single-chip radio is digitally controlled via a standard SPI, and scalable to a phased array architecture. This is the highest level of integration for a 60GHz single-chip transceiver reported till date. The design has been optimized for robustness against process variation and temperature, and verified by measurement results.