{"title":"基于数学形态学的图像处理专用集成电路PIMM1","authors":"J. Klein, R. Peyrard","doi":"10.1109/ASIC.1989.123209","DOIUrl":null,"url":null,"abstract":"To meet image analysis requirements in terms of processing speed and computing capacities, the authors have developed an ASIC (application-specific integrated circuit) with a programmable architecture, supporting the latest algorithms of mathematical morphology. Designed in 1.5- mu m CMOS technology, the ASIC can process 8-b images at a 20-MHz pixel frequency, in pipeline or in parallel. The architecture of PIMM1 is discussed, along with two multiprocessor organizations.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"PIMM1, an image processing ASIC based on mathematical morphology\",\"authors\":\"J. Klein, R. Peyrard\",\"doi\":\"10.1109/ASIC.1989.123209\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To meet image analysis requirements in terms of processing speed and computing capacities, the authors have developed an ASIC (application-specific integrated circuit) with a programmable architecture, supporting the latest algorithms of mathematical morphology. Designed in 1.5- mu m CMOS technology, the ASIC can process 8-b images at a 20-MHz pixel frequency, in pipeline or in parallel. The architecture of PIMM1 is discussed, along with two multiprocessor organizations.<<ETX>>\",\"PeriodicalId\":245997,\"journal\":{\"name\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1989.123209\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123209","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
摘要
为了满足图像分析在处理速度和计算能力方面的要求，作者开发了一种具有可编程架构的专用集成电路(ASIC)，支持最新的数学形态学算法。ASIC采用1.5 μ m CMOS技术设计，可以处理20mhz像素频率的8-b图像，可以流水线或并行处理。讨论了PIMM1的体系结构，以及两个多处理器组织。
PIMM1, an image processing ASIC based on mathematical morphology
To meet image analysis requirements in terms of processing speed and computing capacities, the authors have developed an ASIC (application-specific integrated circuit) with a programmable architecture, supporting the latest algorithms of mathematical morphology. Designed in 1.5- mu m CMOS technology, the ASIC can process 8-b images at a 20-MHz pixel frequency, in pipeline or in parallel. The architecture of PIMM1 is discussed, along with two multiprocessor organizations.<>
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