Yu-Wen Wang, Gwo Giun Chris Lee, Yu-Hsuan Chen, Shih-Yu Chen, Tai-Ping Wang
{"title":"基于卷积Gabor滤波器的深度学习FPGA实现","authors":"Yu-Wen Wang, Gwo Giun Chris Lee, Yu-Hsuan Chen, Shih-Yu Chen, Tai-Ping Wang","doi":"10.1109/RASSE54974.2022.9989881","DOIUrl":null,"url":null,"abstract":"This paper implements an application specific design for calculating the two-dimensional convolution with given Gabor filters onto a Field Programmable Gate Array (FPGA). Nowadays, Convolutional Neural Network (CNN) is a widely used algorithm in the field of computer vision. However, the amount of computation it requires is immense, and therefore special algorithms and hardware are necessary to accelerate the process. We introduce the Eigen-transformation approach, which transforms the 16 Gabor filters into another 16 filters with increased symmetry. This reduces the number of operations, as well as allows us to pre-add the input pixels corresponding to the position of the repeated coefficients. Previous works from our lab analyze the symmetry properties of 7×7 Gabor filters and build the dataflow model of Gabor filter based convolution and use software to implement it. In this paper, we analyze the four models of processing units for the transformed filter bank proposed by the previous work in our lab and use the Xilinx XUPV5-LX110T Evaluation Platform for prototyping. The proposed four models each have unique advantages that make them suitable for different applications. In the experiment, we use a 224×224 image as input and the bit-width of data is 32. Finally, we use the Xilinx Chipscope as an integrated logic analyzer for verification.","PeriodicalId":382440,"journal":{"name":"2022 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Implementation of Gabor Filter Based Convolution for Deep Learning on FPGA\",\"authors\":\"Yu-Wen Wang, Gwo Giun Chris Lee, Yu-Hsuan Chen, Shih-Yu Chen, Tai-Ping Wang\",\"doi\":\"10.1109/RASSE54974.2022.9989881\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper implements an application specific design for calculating the two-dimensional convolution with given Gabor filters onto a Field Programmable Gate Array (FPGA). Nowadays, Convolutional Neural Network (CNN) is a widely used algorithm in the field of computer vision. However, the amount of computation it requires is immense, and therefore special algorithms and hardware are necessary to accelerate the process. We introduce the Eigen-transformation approach, which transforms the 16 Gabor filters into another 16 filters with increased symmetry. This reduces the number of operations, as well as allows us to pre-add the input pixels corresponding to the position of the repeated coefficients. Previous works from our lab analyze the symmetry properties of 7×7 Gabor filters and build the dataflow model of Gabor filter based convolution and use software to implement it. In this paper, we analyze the four models of processing units for the transformed filter bank proposed by the previous work in our lab and use the Xilinx XUPV5-LX110T Evaluation Platform for prototyping. The proposed four models each have unique advantages that make them suitable for different applications. In the experiment, we use a 224×224 image as input and the bit-width of data is 32. Finally, we use the Xilinx Chipscope as an integrated logic analyzer for verification.\",\"PeriodicalId\":382440,\"journal\":{\"name\":\"2022 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RASSE54974.2022.9989881\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RASSE54974.2022.9989881","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of Gabor Filter Based Convolution for Deep Learning on FPGA
This paper implements an application specific design for calculating the two-dimensional convolution with given Gabor filters onto a Field Programmable Gate Array (FPGA). Nowadays, Convolutional Neural Network (CNN) is a widely used algorithm in the field of computer vision. However, the amount of computation it requires is immense, and therefore special algorithms and hardware are necessary to accelerate the process. We introduce the Eigen-transformation approach, which transforms the 16 Gabor filters into another 16 filters with increased symmetry. This reduces the number of operations, as well as allows us to pre-add the input pixels corresponding to the position of the repeated coefficients. Previous works from our lab analyze the symmetry properties of 7×7 Gabor filters and build the dataflow model of Gabor filter based convolution and use software to implement it. In this paper, we analyze the four models of processing units for the transformed filter bank proposed by the previous work in our lab and use the Xilinx XUPV5-LX110T Evaluation Platform for prototyping. The proposed four models each have unique advantages that make them suitable for different applications. In the experiment, we use a 224×224 image as input and the bit-width of data is 32. Finally, we use the Xilinx Chipscope as an integrated logic analyzer for verification.