{"title":"基于期望签名自生成的延迟故障内置自诊断机制","authors":"Yushiro Hiramoto, S. Ohtake, Hiroshi Takahashi","doi":"10.1109/ATS47505.2019.000-4","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a built-in self-diagnosis (BISD) mechanism for delay faults induced by degradation. This mechanism solely generates expected signatures using slower clock on the fly and requires no memory for storing pre-computed expected signatures. In our experiment, the proposed BISD mechanism is applied to benchmark circuits. Area overhead and diagnostic resolution are evaluated.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures\",\"authors\":\"Yushiro Hiramoto, S. Ohtake, Hiroshi Takahashi\",\"doi\":\"10.1109/ATS47505.2019.000-4\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a built-in self-diagnosis (BISD) mechanism for delay faults induced by degradation. This mechanism solely generates expected signatures using slower clock on the fly and requires no memory for storing pre-computed expected signatures. In our experiment, the proposed BISD mechanism is applied to benchmark circuits. Area overhead and diagnostic resolution are evaluated.\",\"PeriodicalId\":258824,\"journal\":{\"name\":\"2019 IEEE 28th Asian Test Symposium (ATS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 28th Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS47505.2019.000-4\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 28th Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS47505.2019.000-4","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures
In this paper, we propose a built-in self-diagnosis (BISD) mechanism for delay faults induced by degradation. This mechanism solely generates expected signatures using slower clock on the fly and requires no memory for storing pre-computed expected signatures. In our experiment, the proposed BISD mechanism is applied to benchmark circuits. Area overhead and diagnostic resolution are evaluated.