An efficient FPGA implementation of AVMF filter using High-Level Synthesis

This paper presents an efficient High-Level Synthesis (HLS) hardware architecture for a floating-point implementation of the AVMF filter using SQRT function. The Vivado HLS tool was used to develop several solutions by adding incrementally various directives to the C code. The validation of our HLS design was realized on the Zedboard platform using a Hardware/Software (HW/SW) environment to estimate the performance. The simulation results prove that the HW/SW design was improved by more than 75% in terms of processing time compared to the SW solution with same image quality.