fpga中基于流水线fppga的缺陷检测(仅摘要)

Lin Meng, K. Matsuyama, Naoto Nojiri, T. Izumi, K. Yamazaki
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摘要

在平板显示器的生产过程中,缺陷的实时检测是非常重要的。本文描述了在现场可编程门阵列(FPGA)上使用带有3线缓冲的4级图像处理管道尽可能快地检测气泡引起的缺陷的方式。图像处理包括读取时延集成(TDI)图像、拉普拉斯滤波、二值化和标记。将TDI应用于FPD的初始图像,以降低FPD图像拍摄时产生的噪声。利用拉普拉斯滤波和二值化对图像进行边缘检测,利用标记对图像中的物体进行编号,进行缺陷检测。在4个阶段的流水线中,第一阶段从块随机存取存储器(BRAM)读取TDI映像,第二阶段实现拉普拉斯滤波和二值化,第三阶段实现标记,最后阶段修改标签并将其写入BRAM。拉普拉斯滤波时需要目标像素及其周围的8个邻居,标记时需要4个邻居。因此,在我们的系统中,三行寄存器(3行缓冲区)被用作两个相邻阶段之间的一般管道寄存器。流水线系统访问这些3行缓冲区并并行运行四个图像处理步骤。因此,系统使用四个不同的地址来访问BRAM和3行缓冲区。此外,为了便于性能比较,我们在FPGA和CPU软件上实现了具有3线缓冲的顺序图像处理系统。实验结果表明,在FPGA上采用4级流水线,可在1 ms内完成FPD缺陷检测的拉普拉斯滤波、二值化和标记,比顺序系统快3.62倍,比CPU软件快158.7倍。就lut的大小而言,管道系统比顺序系统大28%。
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Pipelining FPPGA-based defect detction in FPDs (abstract only)
The real-time detection of defects in Flat-Panel Displays (FPDs) is very important during the production stages. This paper describes the manner in which defects induced by bubbles are detected as fast as possible by using 4-stage image processing pipelines with 3-line buffers on a Field-Programmable Gate Array (FPGA). The image processing consists of reading a Time Delay Integration (TDI) image, Laplacian filtering, binarization, and labeling. TDI is applied to the initial image of the FPD to reduce noises induced when taking the FPD images. Laplacian filtering and binarization are used to detect the edges in the image, and labeling is used to number the objects in the image for defect detection. In the 4-stage pipelining, the first stage reads the TDI image from the Block Random Access Memory (BRAM), the second stage implements Laplacian filtering and binarization, the third stage implements labeling, and the final stage revises the labels and writes them into the BRAM. The target pixel and its eight surrounding neighbors are required during Laplacian filtering, and four neighbors are necessary during labeling. Thus, three line registers (3-line buffer) are used as a general pipeline register between two neighboring stages in our system. The pipelining system accesses these 3-line buffers and runs four image processing steps in parallel. Therefore, the system uses four different addresses to access the BRAM and the 3-line buffers. Further, to facilitate performance comparison, we implemented sequential image processing systems with 3-line buffers on FPGA and CPU software. The experiments reveal that Laplacian filtering, binarization, and labeling for FPD defect detection can be executed in less than 1 ms by using four-stage pipelining on an FPGA, which is 3.62 times faster than the sequential system and 158.7 times faster than the CPU software. The pipelining system is 28% larger as compared to the sequential system in terms of the size of the LUTs.
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