Memory Coherency Based CPU-Cache-FPGA Acceleration Architecture for Cloud Computing

The power efficiency target is becomes the first goal of current hardware system. The workload under cloud computing environment needs to be accelerated by hardware as more as possible, in order to improve the overall power/performance efficiency. The traditional CPU-FPGA architecture can not handle fine granularity routine of algorithm by FPGA hardware in a effective way, as well as challenge on programming model. This paper proposed a memory/cache coherency based CPU-Cache-FPGA architecture to perform an effective transparent communication between software threads on CPU and hardware threads on FPGA. In a sorting application example, the proposed architecture can gain 2.6 times acceleration ratio than traditional CPU-FPGA architecture, as well as a simplified programming model.